Nutaq Technical Frequently Asked Questions

Nutaq Technical Frequently Asked Questions 2017-01-05T19:19:11+00:00

You can find some answers to your technical questions below. Simply select the category for which you need to find an answer, and then select the title of the subject you are interested in to see the detailed question and answer.
(Click to expand or close subjects)

The PicoSDR USB drivers do not install automatically. 2015-07-29T05:06:30+00:00

Manually install the usb driver on your host PC to communicate with your PicoSDR. http://www.ftdichip.com/Drivers/VCP.htm (Other OS) (Windows 7) http://www.ftdichip.com/Drivers/CDM/CDM20830_Setup.exe (Windows 7)

ML605: The BSP example does not run and the print in the console seems to reset. 2015-07-29T05:07:35+00:00

Solution: There is a difference between rev D and rev E board that may cause example to crash. Everything is further explained on the support Xilinx site. http://www.xilinx.com/support/answers/44814.htm

What is the shape factor of the 5-MHz and 20-MHz filters of the RF Tunable low-band module? 2017-01-05T19:19:27+00:00

The following table shows the shape factor of the SFF low-band filters:

SpecificationBPF1BPF2
Center frequency300 MHz300 MHz
Bandwidth5 MHz20 MHz
Insertion lossMaximum of 10 dBMaximum of 10 dB
Pass bandLess than 3 dB (297.5 MHz
and 302.5 MHz)
Less than 3 dB (290 MHz
and 310 MHz)
RippleMaximum of ±0.5 dBMaximum of ±0.5 dB
Stop BandMore than 35 dB (290 MHz
and 310 MHz)
More than 50 dB (270 MHz
and 330 MHz)
More than 20 dB (280 MHz
and 320 MHz)
More than 50 dB (270 MHz
and 330 MHz)
Input/output impedance50 Ω50 Ω

 

What are the transmission and reception gains of the RF Tunable low-band module? 2017-01-05T19:19:27+00:00

The following tables hold the receiver and transmitter information.

What is the maximum input power that the RX path can sustain? 2015-07-29T05:15:16+00:00

The maximum input power is –25 dBm for the Low-Band RF Module and the High-Band RF Module.

Is it possible to use other antennas than the ones supplied? 2015-07-29T05:12:14+00:00

Yes, you can connect any other antenna to your SFF SDR development platform.
The RF Tunable module is equipped with standard female SMA connectors. The choice of the antennas is application (waveform) specific, so please make your choice carefully if you use other antennas than the ones supplied.

How long does the oscillator of the RF Tunable low-band module take to settle? 2015-07-29T05:13:11+00:00

It takes between 240 µs and 420 µs to switch frequencies (programming time excluded).

What is the amplifier used for the programmable reception gain? 2015-07-29T05:34:42+00:00

You can adjust the signal level through the Peregrine Semiconductor PE4305 programmable attenuator and the Linear Technology LT5514 programmable gain amplifier.

What is the phase noise of the RF Tunable low-band module? 2017-01-05T19:19:27+00:00

The following results were obtained with an RF Tunable low-band module configured at 425 MHz (carrier).

DirectionOffsetSpecification
RX10 kHz–75 dBc/Hz
RX100 kHz–103 dBc/Hz
TX10 kHz–83 dBc/Hz
TX100 kHz–109 dBc/Hz

 

What is the reception noise figure of the RF Tunable low-band module? 2015-07-29T05:15:12+00:00

Module:  RF TUNABLE LOW BAND

The typical noise figure of the RF Tunable low-band module RX channel is 5 dB.

Is it possible to transmit and receive simultaneously on the RF Tunable modules? 2015-07-29T05:17:29+00:00

Yes, all supported RF Tunable modules can simultaneously transmit and receive as they support a full-duplex communication. Note that the TX and RX frequencies could be programmed independently.
 

How many channels are available for the RF Tunable modules? 2015-07-29T05:16:24+00:00

The RF module is equipped with one transmission channel and one reception channel.

What is the frequency range of the antennas supplied with RF Tunable low-band module? 2015-07-29T05:18:19+00:00

The antennas currently supplied with an SFF SDR development platform are adjusted to operate between 410 MHz and 512 MHz, covering the FRS and GMRS bands.

How is the RF Tunable low-band module controlled? 2015-07-29T05:19:38+00:00

The RF Tunable low-band module can be controlled with the functions of the board software development kit (BSDK) or the model-based development kit (MBDK) associated with your product.

What are the nominal levels of the ADCs and DACs? 2017-01-05T19:19:27+00:00

The following table shows the ADC’s nominal levels:

The following table shows the DAC's nominal levels:

Is there usable RAM on the ADACMaster III? 2015-07-29T05:21:14+00:00

There is no RAM available for users on the ADACMaster III.

Is there analog automatic gain control before the analog-to-digital converters? 2015-07-29T05:22:18+00:00

No, the gain control before the ADCs is programmed by the user-defined software; there is no automatic gain control mechanism.

Are the ADC and DAC clocks independent? 2015-07-29T05:23:39+00:00

No, the ADC and DAC clocks may have different frequencies, but there must be an integer ratio between them as they are derived from the same clock source.

Is it possible to implement signal processing in the FPGA of the ADACMaster III? 2015-07-29T05:23:02+00:00

Yes, a separate license is offered to target the FPGA of the ADACMaster III either in the BSDK or the MBDK design flows. Contact Nutaq for details.

How to know if the acquired signal is out of range? 2015-07-29T05:24:28+00:00

A red LED at the front of the ADACMaster III (on the same side as the ADC connectors) indicates whether the ADC is saturated.
The ADACMaster III BSDK and MBDK packages (with the required license) allow the user to use an ADC over-range signal in the design logic.

How is the ADACMaster III module controlled? 2015-07-29T05:25:08+00:00

The ADACMaster III module can be controlled with the functions of the board software development kit (BSDK) and the model-based development kit (MBDK) associated to your product. A specific license for these packages must be purchased.

What is the capacity of the FPGA before waveform functions are added? 2017-01-05T19:19:27+00:00

The following table shows the default design resource allocation.

ResourceUsedAccessible% of use
Slices± 2,0215.36013
DCM3837
BUFG93228
RAMB1621921
DSP4811921

 

 

Is the MULTI IDE from Green Hills Software essential to develop applications on the SFF SDR development platforms? 2015-07-29T05:27:36+00:00

No, it is not necessary.
The MULTI integrated development environment and tools suite from Green Hills Software can be used to target the ARM portion of the DM6446 running the INTEGRITY RTOS.

Is it possible to run a Linux kernel on the ARM? 2015-07-29T05:29:17+00:00

Yes, a community (ossie.wireless.vt.edu/trac/wiki/SffsdrLinux) offers open source SFF SDR development platform drivers for Linux and the Open Source SCA Implementation ::Embedded (OSSIE).

Important: Read carefully before proceeding and proceed at your own risk. Nutaq offers no support for these software products because they are not supplied by Nutaq.

Is it possible to recompile the INTEGRITY OS kernel? 2015-07-29T05:28:26+00:00

Yes, an INTEGRITY kernel BSP is supplied with the software accompanying your product.

What JTAG emulator should I use to target the DSP? 2015-07-29T05:30:20+00:00

The DM6446 JTAG interface on the SFF SDR development platform or evaluation module is a 1.8-V, 14-pin connector. Nutaq recommends using one of the following JTAG emulators to interface with the DSP core of the DM6446:
+ Spectrum Digital XDS510 USB JTAG emulator. This emulator is 3.3-V and 5-V compatible. It requires using a voltage shifter to be 1.8-V compatible.
+ Spectrum Digital XDS510 USB PLUS JTAG emulator with 14-pin target adapter cable.
+ Spectrum Digital XDS510PP PLUS JTAG scan path emulator pod.
+ Spectrum Digital XDS560R USB JTAG emulator with 14-pin JTAG header.
Other JTAG emulators compatible with the DM6446 DM SoC core should also function adequately.

Is it possible to interface expansion boards with the digital processing module? 2015-07-29T05:35:11+00:00

Yes, Nutaq offers boards that interface with the digital processing module.
The ADACMaster III module interfaces through the expansion connector.
The RF modules interface through the GPIO connector and can also be connected to the ADACMaster III through the SMA connectors. The supported RF modules are:
+ The Low-Band Tunable RF Module
+ The High-Band Tunable RF Module
+  The 2.5 GHz WIMAX Wideband RF Module
+ The 2.5 GHz WIMAX Narrowband RF Module
No other expansion boards are developed by Nutaq at this time. It is however possible for you to design your own expansion board and connect it through the expansion connector or the GPIO.

What are the possible transfer rates between the DSP and the FPGA? 2015-07-29T05:36:02+00:00

Possible transfer rates depend on the type of development that you are performing and also on the type of design that you are implementing (in terms of bandwidth, throughput, and data formatting). Benchmarks show possible transfer rates reaching 20 MBps with language-based development.
Note: Refer to the SFF SDR User’s guide for details on how to achieve this transfer rate.

What processors can be targeted through the model-based design flow (MBDK)? 2015-07-29T05:36:48+00:00

The DSP portion of the DM6446, the Virtex-4 SX35 FPGA of the digital processing module, and the Virtex-4 FPGA of the ADACMaster III can all be targeted through this development method.

Can the SDRAM be upgraded beyond 128 MB? 2015-07-29T05:37:39+00:00

No, the DDR2 SDRAM cannot be upgraded beyond 128 MB.

Can the SD memory card be used for data recording purposes? 2015-07-29T05:38:48+00:00

No, the SD memory card is not supported.

How many RF modules can simultaneously be interfaced to an SFF SDR development platform? 2015-07-29T05:39:32+00:00

The ADACMaster IIIof a SFF SDR development platform has two RX channels (ADCs) and two TX channels (DACs). Therefore, the number of RF modules that can simultaneously be interfaced to a SFF SDR depends on the number of RX/TX channels your RF module needs.
Examples:
A. Low-band and High-band RF modules use 1 ADC channel and 2 DAC channels; therefore, only 1 module can be used at a time.
B. WiMAX RF modules use 1 ADC channel and 1 DAC channel; therefore, 2 RF modules can be used simultaneously.
 

What are the controllable components and interfaces of the SFF SDR development platforms? 2017-01-05T19:19:27+00:00

The following list of components and interfaces can be controlled with both the BSDK and MBDK design flows:
+ Audio codec
+ LED
+ Push buttons
+ DIP switches
+ DSP-FPGA data bus

What is the purpose of the ARM on the SFF SDR processing board? 2015-07-29T05:41:05+00:00

The ARM runs the INTEGRITY RTOS which includes:
+ Start-up sequence and initialization
+ Ethernet management
+ Central communications engine (CCE)
+ ARM/MSP430 communications (manages power monitoring)
+ File system management
 

What processors can be targeted through the language-based design flow (BSDK)? 2017-01-05T19:19:27+00:00

The targetable processors are:
+ The ARM and DSP portion of the DM6446 chip.
+ The Virtex-4 SX35 FPGA of the digital processing module.
+ The Virtex-4 FPGA of the data conversion module.
 

The PLL doesn’t lock when all clocks are set to 30.72 MHz (revisions C and D). 2015-07-29T05:43:04+00:00

When the required clocks are all set to 30.72 MHz, the PLL is bypassed and therefore does not lock since it is not used.

Are the SFF SDR development platforms offered with different FPGA? 2015-07-29T05:43:50+00:00

The digital processing module is not offered with FPGA models other than the Virtex-4 SX35 in the case of single-unit orders. In the case of bulk orders; however, Nutaq can accommodate. Contact Nutaq for details.
The ADACMaster III is now only offered with Virtex-4 SX35 FPGA.

How much processing power does the digital processing module deliver? 2015-07-29T05:44:54+00:00

The C64+ DSP core can process 4,752 8-bit MMAC or 2,376 16-bit MMAC at 594 MHz. The SX35 Virtex-4 FPGA has 15,360 CLB slices, 192 18-kilobit blocks of RAM, and 192 XtremeDSP slices.

My FPGA design must run at a specific frequency. How can I configure the Radio420x to obtain the wanted design clock? 2015-07-29T05:45:37+00:00

In a Radio420x FPGA design, the design clock is typically the clock received from the Radio420 on FMCCLK0. This clock is set to the same frequency as the Radio420's ADCs and DACs. To run the design at a specific frequency, the Radio420's ADC and DAC clock must be initialized to that frequency.
For example, in the Radio420 Record/Playback example, the ADC/DAC frequency is set (to 40.96MHz) using this define:
#define ACQUISTION_FREQ FMCRADIO_DATARATE_REF_30_72MHZ_40DOT96MHZ

To change the design clock frequency, simply replace FMCRADIO_DATARATE_REF_30_72MHZ_40DOT96MHZ with the frequency value in samples per second.
ex.: #define ACQUISTION_FREQ 10000000
Note: The ADC and DAC frequency is set at the number of I samples + Q samples per seconds sent or received. Therefore, if the design expects 10 million I samples and 10 million Q samples per second, the frequency should be set to 20000000.

When running a Radio 420x example, I obtain an RX DC offset calibration failure. What is causing the failure and how can I solve it? 2015-07-29T05:46:26+00:00

During the RX DC offset calibration, the FPGA averages the signal received to calibrate the DC offset. Typically, when an error occurs, it is because the acquired signal saturates at the ADC and is clipped when sampled in the FPGA. Reduce the power inputted to the Radio 420 RX or reduce the RX gain to avoid signal saturati

The frequency generated by the Radio420s loopback example described in the functional example section of the Perseus User’s guide is not the expected frequency. 2015-07-29T05:47:43+00:00

ADP software versions 5.5.0 and prior do not correctly support the Radio420x revisions C and D. You should update your ADP software to version 5.6.0 or later to use them. The revision B board is correctly supported by versions 5.5.0 and prior.

Error loading the program in a Debug session. 2017-01-05T19:19:27+00:00

When starting a Debug session in XSDK, the program cannot be loaded into the memory and the following error message is displayed:

How can this problem be solved?

Answer:
When this happens, disconnect the JTAG USB cable, close SDK, and turn off the ML605.
Make sure all SDK processes are stopped after closing the SDK window. Sometimes, javaw.exe software is still running and must be close manually in the Windows Task Manager dialog box.

Make sure the DDR3 SODIMM memory is correctly connected to the ML605. To do so, remove the DDR3 SODIMM memory and insert it back.
Turn on the ML605, connect the JTAG USB cable, and reopen SDK.
Program the FPGA with the generated bitstream.
Starting a Debug session should now work.

On an MI125-32 stack (two MI125 FMC), how can the external clock and external trigger be used? 2015-07-29T05:49:19+00:00

On an MI125-32 stack, the external clock and trigger must be connected to the card sitting directly on the carrier (MI125-16E). This card is the clock master for the stack.

What is the benchmarked throughput of the PCI Express RTDEx? 2015-07-29T05:50:03+00:00

The maximum throughputs obtained are:

From the embedded processor blade to the FPGA: 543 MBytes/second
From the FPGA to the embedded processor blade: 265 MBytes/second
These benchmarked values were obtained using a Perseus revision C and an SAMC-514 processor (Fedora 17) in a VT852 Vadatech chassis, running the PCI Express RTDEx example from the ADP release 6.1.

How can I read/write to the ADC, DAC, or PLL chips? 2015-07-29T05:51:49+00:00

To read/write from/to the ADC, put the following pins to the specified levels:
+ ADC SPI Enable = E3 Low (access enabled)
+ DAC SPI Enable = E2 High (access disabled)
+ PLL SPI Enable = F5 High (access disabled)
To read/write from/to the DAC or PLL, put the ADC SPI Enable to High and the corresponding Enable pin to Low. Make sure there is only one pin Low and the other two High.

I am able to read/write values in the DAC5682Z chip, but not in the ADS62P49 chip. Why is that? 2015-07-29T05:50:49+00:00

The F4 SPI_SDO pin is linked to all SPI chips of the ADAC250 and routing of the SDO signal is switched by the chip select pins. Make sure all chip select are high except the ADC chip select (E3 pin) and try to read a known value. You can also try to write then read back a value.

Are there FPGA pins not supported in the BSDK and MBDK packages? 2017-01-05T19:19:27+00:00

The following pins are not used in the software packages:

PinPin numberDirectionType
AVR_RXDAW35INLVCMOS25
AVR_TXDAY34OUTLVCMOS25
E_KEY0_FPGAD15INOUTLVCMOS25
E_KEY1_FPGAC15INOUTLVCMOS25
E_KEY2_FPGAG12INOUTLVCMOS25
E_KEY3_FPGAH13INOUTLVCMOS25
CUSTOM0_FPGA_IOF15OUTLVCMOS25
CUSTOM1_FPGA_IOAW16OUTLVCMOS25

AVR_RXD and AVR_TXD are UART links RX and TX between the FPGA and the AVR.
The other pins are either GPIO pins or a SPI link between the FPGA and the AVR. There is also no code on the AVR that uses these pins.

 

System does not boot after flashing the FPGA bitstream on Perseus. 2017-01-05T19:19:27+00:00

I tried to program the bitstream application into the flash of the Perseus. However, the system does not boot anymore and shows following the error message.

Answer:
The Uboot and Linux kernel has been corrupted or erased. Please proceed as follows.
+ Get a copy of the u-boot.elf file and put it in the ‘c:’ folder.
+ Connect the JTAG programmer to the Perseus.
+ Connect to the Perseus serial port using Putty.
+ Open Xilinx Platform Studio.
+ In the menu go to Debug> Launch XMD.
+ When XMD is open enter the following commands:
"connect mb mdm"
"dow c:/u-boot.elf"
"run"
The Perseus should reboot and start properly. Perform the "Programming the Linux firmware in the flash memory" procedure (in Perseus User’s guide refer to the section on programming the Linux firmware in the flash memory) with the ‘u-boot-s.bin’ and ‘u-boot.elf’ files located in your ‘ADPROOTfpgabin’ folder.
Do not forget to replace ‘ADPROOT’ by the path where you installed the ADP software.

The XPS project refuses to open and prints errors in the XPS console. 2015-07-29T05:54:24+00:00

WARNING: EDK:1687 – Invalid path specified for ModuleSearchPath in XMP file. Please make sure that the directory specified exists.
ERROR: EDK: 4110 – IPNAME: lyt_axi_emac_rtdex, INSTANCE: axi_emac_rtdex – cannot find MPD for the pcore “lyt_axi_emac_rtdex_v1_00_a” in any of the repositories –
C:testexamples_perseus6010perseus6010_radio420x_rtdex_record_playbackedkperseus6010_radio420x_record_playback.mhs line 493.
WARNING: EDK:4264 – elf file specified with tag ElfImp: C:testfpgabinperseus601x_default_linux.elf not found INFO:EDK – Resetting ElfImp tag in the project file…
WARNING: EDK:3362 – Cannot open project due to errors.

Answer:
The XPS projects use relative paths to find the required files. If the project file was moved to a different folder, in or out of the ADP installation hierarchy, the project will not find the files and will not be able to open them.

What are the PC requirements to develop with Xilinx tools? 2015-07-29T05:56:01+00:00

It is recommended to use Windows 7 (64-bits) and have at least 10 GB of RAM.

Does Nutaq provide VHDL reference design for its FMC cards used on other industry FMC carriers? 2015-07-29T05:56:45+00:00

Yes, please consult the software development tools section on our Web site. 

When trying to program the FPGA in XSDK, the progress bar is not progressing. 2017-01-05T19:19:27+00:00

The JTAG driver is being held by another instance of a Xilinx program. When it happens, disconnect the JTAG USB cable, close SDK, and turn off the Perseus.
Make sure all SDK processes are stopped after closing the SDK window. Sometimes, javaw.exe software is still running and must be close manually in the Windows Task Manager dialog box.

Turn on the Perseus, connect the JTAG USB cable, and reopen SDK. FPGA programming should now work.

 

When trying to program the FPGA in XSDK, the progress bar is not progressing. 2015-07-29T05:58:11+00:00

In Visual Studio, when building an example in a 64-bit configuration, the project build is skipped and nothing happens.

Answer:
To compile a 64-bit project with Visual Studio, you must select the X64 Compilers and Tools check box during the Visual Studio installation.
 

How can I build a MicroBlaze C program for a bitstream generated in MBDK/System Generator? 2015-07-29T05:58:55+00:00

Nutaq does not support the build of custom C programs for the MicroBlaze in MBDK generated bitstreams. However, the following can help you setup your XSDK project.
– The MBDK model cannot use any BSDK or MBDK functionality. Make sure no RTDEx or Record/Playback blocks is present in the model.
– Compile the MBDK model (for the purpose of this example, the target directory is …/work/test_sdk in System Generator).
– Once the compilation is successful, open the generated .xmp file at this location: …worktest_sdkperseus601x_sysgenperseus601x_sysgen.xmp.
This will generate the system.xml temporary file: …worktest_sdkperseus601x_sysgen__xpssystem.xml
– Copy it somewhere else since it is in a temporary folder.
– Open XSDK and create a new workspace.
– In XSDK, create a new Hardware Platform Specification, select the system.xml file, and select the bitstream and BMM files found in
…worktest_sdkxflowperseus601x_sysgen.bit
…worktest_sdkxflowperseus601x_sysgen_bd.bmm
– After the Hardware Platform Specification is created, this becomes like any other XSDK project.

When compiling a Visual Studio project, the following error occurs: C1047: The object or library file …xxx_win64.lib was created with an older compiler than other objects; rebuild old objects and libraries. 2015-07-29T06:00:02+00:00

For the ADP releases 6.0 or later, all libraries were compiled with Visual Studio 2008 SP1. Make sure you have Visual Studio 2008 with Service Pack 1 installed. You can download the service pack at http://www.microsoft.comhttps://www.nutaq.com-us/download/details.aspx?id=13276

System Generator produces an error: Failed to implement the design as it could not meet one constraint. 2017-01-05T19:19:29+00:00

To solve this problem, lower the clock frequency of the design or add some registers in the critical path.

 

After upgrading the ADP version, I get an error while compiling a project made from an old release. 2015-07-29T06:01:24+00:00

After upgrading the ADP version, I get an error while compiling a project made from an old ADP version. The error are of the type ERROR:PhysDesignRules:xxxx. For example:
ERROR:PhysDesignRules:2399 – The GTXE1 comp ETH0_MAC/ETH0_MAC/V6HARD_SYS.I_TEMAC/I_EMAC_TOP/EmacBlock_l/GTP_DUAL_1000X_inst/rocketio_wrapper_inst/gtx0_rocketio_w rapper_i/gtxe1_i has POWER_SAVE[4] set to an unsupported value and must be set to 1. Please see Answer Record 39430 for more information.

Answer:
Delete the work directory to erase all files compiled with the previous version.

What memory devices are on the Perseus and what is their usage? 2017-01-05T19:19:29+00:00

8-bit DDR3 SDRAM: Dedicated to the uBlaze CPU to use as a program memory either for:
a) an OS (for example, Linux)
b) a standalone C program that is too big to fit in the FPGA internal BRAM.
1G SODIMM:
Used for the record-playback module for data acquisition and storage.
It can also be used to store acquired data before being sent to the host via the RTDEx communication channel.
FLASH Memory:
Used to permanently store the FPGA bitstream, the Linux kernel, and U-boot images.

How to program a bitstream file in the flash memory? 2015-07-29T06:03:46+00:00

It is possible to flash the bit file to make it permanent:
+ Start the ADP CLI software.
+ Connect to the board with the command: connect your.board.ip.address (for example, connect 192.168.0.1).
+ Download your bit file to the flash using the command: fpgaflash filename.bit.
Note: The easiest way to enter the bitstream.filename is to drag and drop the Windows File Icon to the ADP CLI window after entering the fpgaflash command followed by a space.
The fpgaflash command will download the bit file and save it in the onboard flash memory.
Your bitstream should be running the next time you start the board.

How to resolve the error number 0x80040707 description: DLL function call crashed: Lybarlog. GetNICMAC? 2015-07-29T06:04:54+00:00

This is a known issue from the license manager function that retrieves the MAC address in Windows 7, 64 bits. This happens when there are a lot of local area connections for the tunnel adapters on your computer. This can be confirmed using the “ipconfig –all” command in a command prompt. To resolve the problem, the connections have to be removed. To do so:
1) Open the device manager.
2) Select View/Show hidden devices.
3) Scroll down to the network adapters.
4) Right click and uninstall all but 1 of the tunnel adapters.

Where should I upload the .req file while doing an offline installation? 2015-07-29T06:05:35+00:00

The .req file needs to be uploaded at the http://license.nutaq.com/act_server/offline/  address. From there you will get the .ans file required to continue offline installation.
 

What FPGA JTAG does Nutaq recommend for its hardware platforms? 2015-07-29T06:06:24+00:00

Nutaq recommends the Xilinx Platform Cable USB II, model number DLC10. You can find information about it on the Xilinx web page at http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm. 

Is it possible to have access to the board schematic? 2015-08-10T11:22:07+00:00

No, unfortunately Nutaq does not provide board schematic.

C​an the Nutaq FMC cards be used on other FMC carriers than Nutaq’s? 2015-07-29T06:07:50+00:00

Yes, please consult Nutaq's FMC card product sheet specifications to validate FMC requirements. 

How can the ADP error codes (ex.: adp_exception 0xXXXXXXXX) be interpreted? 2015-07-29T06:08:48+00:00

The error code is divided in three sections: the severity of the error, the module causing the error and the error itself. The following procedure illustrates how to find the error code meaning (in this case, error 0xC0640006)
Error severity: In the file %ADPROOT%sdklyt_std_libinclyr_error.h, in the ADP installation, is the enumeration Lyr_Severity. The 2 MSBs of the error code are set by the severity enumeration. Here, 0xC indicates an error (severity level is 3).
Error module: In the file %ADPROOT%sdklyt_std_libinclyr_error.h, in the ADP installation, is the enumeration Module. Bits 16 to 30 of the error code are set by this enumeration. Here, the 0x064 indicates an error from the Radio420 driver.
Error: When the error module is know, browse to the module's types headers file to find the error name. In this case, the Radio420 error enumeration is available in the fmc_radio.h file at this location %ADPROOT%sdkfmcradio_libinc in the ADP installation. Bits 0 to 15 of the error code are set by the error enumeration. Here, 0x0006 indicates that the RX DC calibration failed.

When compiling an example in Visual Studio, I get an error due to missing libraries xxx_win32.lib. 2015-07-29T06:09:27+00:00

ADP releases 5.6.0 and later do not support 32-bit projects on Windows. You must compile the project with the option Release x64. If you do not have this option, you should reinstall Visual Studio with the 64-bit compiler tools.

When using the CLI software to initialize the Perseus, the CLI freezes when calling ram_get. 2015-07-29T05:01:17+00:00

This problem has been resolved for ADP version 6.0 and later.
For version 5.6 and earlier, this error occurred when the host had not received the specified data size and was waiting for more data.
Make sure that the MAC addresses specified in the ram get line are valid. The generic MAC addresses (host and Perseus) in the example provided with the installation must be replaced with the actual MAC addresses of your system.
Make sure there is no firewall or antivirus software running on the host computer that could impede packet transfers.

I get an error retrieving recorded data from the Perseus memory. What causes the error and how can I avoid it? 2015-07-29T06:10:31+00:00

Two types of error can occur: When, in the examples, the error is “WARNING: transfer frames lost:”, it means that an RTDEx packet was lost between the FPGA and the host. Make sure the Perseus is connected directly to the host computer (no Ethernet switches external to the chassis). It is also possible that the host computer cannot handle the speed of the transfer from the FPGA. To slow the transfer, set the frame gap to a higher value. For example, #define FRAME_GAP 200000.
 
When, in the examples, the error is “WARNING: transfer not completed because of a small timeout”, it means that not all the expected packets were received but no packets were lost. The causes for this can be an incorrect configured RTDEx and Record/Playback cores (for example, trying to receive more packets than previously indicated in the RTDExStart function) or it can be a bad connection between the RTDEx and Record/Playback cores in the FPGA. The RTDExReceive function returns the number of bytes received, which can help you find the cause of the problem.