RF Specification

Receiver

RF InputMMCX (50 Ω)

2×2 : 2 Channels

2×2-E (With CPU) : 2 Channels

4×4 : 4 Channels

ArchitectureZero-IF (direct conversion)
Tuning range300 MHz to 3800 MHz
Frequency resolution2.4 Hz
PLL settling time20μs + FPGA Programmation (I2C)
Pre-select RF filter bank14x Selectable RF band pass filters or Bypass mode
Baseband configurable low-pass filter0.75 MHz to 14 MHz
(RF channel bandwidths from 1.5 MHz to 28 MHz)
Typical noise figure10 dB
IMD3Low band: -61 dBc to -56 dBc

High band: -50 dBc to -45 dBc

Wideband noise floor-100 dBFS
Sensitivity (SNR=5 dB and bandwidth=200 kHz)Low band: -103 dBm

High band: -90 dBm

Gain control rangeLow band: 79 dB

High band: 73 dB

Absolute maximum input power-13 dBm
I/Q balancingAuto-Calibrated (Software Provided)
SFDR50 dBc

Transmitter

RF OutputMMCX (50 Ω)

2×2 : 2 Channels

2×2-E (With CPU) : 2 Channels

4×4 : 4 Channels

ArchitectureZero-IF (direct conversion)
Tuning range300 MHz to 3800 MHz
Frequency resolution2.4 Hz
PLL settling time20μs + FPGA Programmation (I2C)
Baseband configurable low-pass filter0.75 MHz to 14 MHz
(RF channel bandwidths from 1.5 MHz to 28 MHz)
Output: IMD3-60 dBc
Wideband noise floor-124 dBc/Hz
SpurInband: -100 dBc

Adjacent channel: -60 dBc

Total gain control70 dB
P1 db outputLow band: 10 dBm (typical)

High band: 5 dBm (typical

Typical carrier suppression-50 dBc
Sideband suppression-45 dBc

Digital Specification

CPUOption: Intel Quad-core i7 Gen2 CPU, 2.1 GHz processor)
FPGAOption 0: Xilinx® Virtex®-6 LX240T
Option 1: Xilinx® Virtex®-6 LX550T

Option 2: Xilinx® Virtex®-6 SX315T
Option 3: Xilinx® Virtex®-6 SX475T

Non-volatile memory64 MB (FPGA)

64 GB + SATA expansions (CPU)

RAM4 GB DDR3 (FPGA)

18 MB QDR2 (FPGA)

128 MB DDR3 (FPGA)

8 GB DDR3 (CPU)

Operating SystemLinux (Ubuntu/Debian/Fedora)

Windows (Win7)

System InterfaceGigE, PCIe, USB Consol, JTAG, USB (CPU Option), SATA (CPU Option), HDMI (CPU Option)
Radio (FPGA-CPU) Data LinkGigE (900 Mbps sustained throughput)

PCIe 4x (6.4 Gbps sustained throughput)

Typical Power Consumption2×2 : 35 W (Min : 3 W)

2×2-E (With CPU) : 55 W (Min : 3 W)

4×4 : 70 W (Min : 3 W)

System Reference Clock Specification

TypeVoltage Controlled Crystal Oscillator (TCVCXO)
Frequency30.72 MHz
Frequency Accuracy2 ppm
Frequency Warpingusing on-board D/A converter (16-bit)
GPS-DisciplinedUsing an external PPS Input (FPGA control) MMCX
Alternate Clock Input OptionExternal clock/reference input on MMCX
Clock OutputUser selected Clock on MMCX, used for multi radio-head daisy-chain synchronisation

Power Supply

PicoSDR supply input12 VDC
Provided External PSUUniversal 100-240 VAC

Physical Specification

Dimensionsh: 48 mm, w: 215 mm, d: 290 mm
Weight2×2 : 2.4 Kg

2×2-E : 2.6 Kg

4×4 : 2.4 Kg