Nutaq provides its customers with two different design flows, namely, Model-Based Design Kit (MBDK) and Board Software Development Kit (BSDK). For each of these design flows, Nutaq provides custom block-sets (MBDK) and IP cores (BSDK), that are used to access different hardware peripherals onboard the system, including the radio FMCs, the ADCs, the DACs, the 4GB DDR3 SODIMM RAM, etc. These custom blocks and IP cores are designed to work with various IP cores and System Generator block-sets provided with Xilinx. Generally, customers that are interested in rapid prototyping with little to zero FPGA experience prefer MBDK, while those with advanced FPGA experience tend to do all their designing in BSDK. For each of these design flows, there are ways through which customers can integrate their custom VHDL and Verilog codes in their designs. In this brief application note, we show how to integrate a custom VHDL code in MBDK and BSDK design environment. To this end, we will utilize a simple AND logic code, written in VHDL, and integrate it into MBDK and BSDK design environment. The VHDL code is shown below:
entity and_gate_custom is
Port ( First_input : in STD_LOGIC_VECTOR (15 downto 0);
Second_input : in STD_LOGIC_VECTOR (15 downto 0);
Output_Final : out STD_LOGIC_VECTOR (15 downto 0));
architecture Behavioral of and_gate_custom is
Output_Final <= First_input and Second_input;
Integration into MBDK Design Flow:
To integrate the above code in MBDK, we will utilize the Black Box block provided by Xilinx. The block can be accessed through Simulink Library Browser, as shown below:
When this block is dragged and dropped into the design environment, the user automatically gets a prompt window asking for the location of the VHDL or Verilog file, as shown in Fig. 2 below. At this stage, the user can select the file that is to be used for the blackbox. Once the required VHDL file is selected, Black Box block automatically generates a corresponding mcode for the block, as shown in Fig. 3. Further, one can also see the input and output ports of the block in Simulink model environment, as shown in Fig. 4. The I/O ports follow the same name as those declared in the original HDL code outlined above. At this stage, it is imperative to mention that the Black Box, by default, always declares the input and output vectors as Ufix (unfixed) with no binary point, as shown in Fig. 3. Users can directly change the I/O to the desired format and binary point location by changing the generated mcode file shown in Fig. 3. Following this procedure, the user’s custom HDL code has been successfully imported into the design and the inputs and outputs can be connected to rest of the design.
Integration into BSDK Design Flow:
With the BSDK design flow, it is always recommended that users build on top of existing examples that Nutaq provides. That way, all the Nutaq IP cores are already imported into the project. If one were to start building in Xilinx Platform Studio (XPS) from scratch, they would have to import all of Nutaq IP cores one by one. In view of this recommendation, we will open one of the existing Nutaq BSDK examples and import the same AND gate code into an existing project. To this end, Fig. 5 shows an example project, which comes as part of Nutaq Board and Software (BAS) design suite. In this environment, all of Nutaq IP cores can be found in the IP Catalog window, under the Project Peripheral Repository, as shown in Fig. 6.
In order to import the custom VDHL code as an IP core, the first step is to select Create or Import Peripheral under Hardware drop-down menu, as shown in Fig. 7. This launches the wizard to import the peripheral.
After selecting Next on the welcome window of the Create or Import Peripheral Wizard, users are given the choice of creating a new peripheral or of importing an existing one. For this example, we will select an existing peripheral, as shown in the Fig. 8 below.
Clicking Next at this stage, the Wizard allows the user to specify whether the new peripheral should be available universally, for all future EDK designs, or for the specific XPS project which is open at the moment. Here, we will only import the peripheral locally, for the opened project, as shown below.
The next step is to enter the name of the top VHDL entity or Verilog module. This name should be the same as the name of the VHDL file, which in our case, is “and_gate_custom”, as shown above in Fig. 2. At this stage, we can also select a version number for the IP core. This enables the user to keep track of various versions of the core, in case different versions of the core are imported during the development process. All these details are shown in Fig. 10.
Following this, the users can indicate the type of files that make up the peripheral. For the sake of this example, we will only select HDL source files option, since we are only importing a single VHDL file. Next, the Wizard allows the users to specify how to get the source file, as shown in the figure below.
In the next step, we add the HDL file, following which, the Wizard enquires whether or not the user wants to connect the peripheral directly to the AXI bus. For this example, we will not be connecting our custom IP core to the AXI bus, leaving that step for a future blog post. Upon clicking Next, the Wizard allows the user to make any of the peripheral I/O ports interrupt sensitive. Following this, users can specify special attributes for the I/O ports. For the purpose of this example, we will skip these last two steps. At the final step, the Wizard provides a summary of the peripheral, as shown below. Clicking Finish imports the new peripheral into the project, as a custom IP core.
The newly imported peripheral is now available for use. It can be found in IP catalog window under Project Local Cores, as shown in the figure below.
In part two of this blog post, we will show how the user can connect a new peripheral to the AXI bus and then import it into the project as a new IP core.
07-19-2016, Auon Akhtar, PhD, Field Application Engineer