Introduction

The Nutaq ZeptoSDR platform offers a complete solution for software-defined radio (SDR) application development. The ZeptoSDR consists of a Radio420S FPGA mezzanine card (FMC), an RF transceiver, and a ZedBoard baseboard within an air-cooled enclosure.

The ZedBoard has a community-based website with lots of tutorials and reference designs. In addition, ZeptoSDR users can benefit from the Nutaq reference designs and API when performing rapid application development.

This blog post explains the architecture of the different Nutaq reference designs as well as the APIs.

Figure 1: ZedBoard platform

Figure 1: ZedBoard platform

Figure 2: Radios420S FMC

Figure 2: Radios420S FMC

Board Support Package (BSP)

The example included with the BSP shows how to send and receive data between the Radio420S FMC and the FPGA logic and how to configure the Radio420S with the embedded processor. On the Zedboard, all these operations are done by the Zynq system-on-chip (SoC) as it has a dual ARM Cortex-A9 processor and programmable FPGA logic.

The BSP example lets the user develop applications with the architecture shown in Figure 3.

Figure 3: BSP application architecture

Figure 3: BSP application architecture

In the FPGA section of the Zynq, a Radio420 FPGA core is used for configuring the FMC and for RF data transfer. The FPGA core has input and output ports that enable FPGA user logic to send and receive data with the radio front-end. In the example, a Direct Digital Synthesizer (DDS) core in the user logic sends data to the Radio420. A Chipscope core in the user logic receives the data and displays it to the user. All communication protocols within the Radio420S FMC are controlled by the Radio420 core.

The AXI Lite protocol manages communication between the ARM and the Radio420 FPGA core. All the Radio420 core registers are mapped to the Zynq memory space. An API is provided to simplify configuration of the Radio420S FMC chips and the Radio420 FPGA core. The API can be called by a user application that runs on the ARM processor. All the low-level logic and register accesses for chip configuration are handled by the API, making high-level functions available to the user.

See the Radio Peripheral Configuration section of the blog post,

[Comparison: Nutaq API and USRP Hardware Driver], for overview of the API functions.

Board Support Development Kit (BSDK)

The example included in the BSDK uses the same Radio420 FPGA core and API as the BSP. The main difference is that the ARM processor runs a Linux distribution to provide access to common peripherals like Ethernet and to a real-time data exchange (RTDEx) interface between the FPGA logic and the processor memory.

An AXI RTDEx FPGA core implements “first in/first out” (FIFO) memory in both directions when interfacing with the rest of the FPGA logic. On the processor side, a driver has been developed to ease the data transfer. A device is available and simple write and read operations allow data exchange with the programmable logic. The RTDEx implementation uses the PL330 DMA driver available in the Zynq and converts the resulting AXI protocol transactions into FIFO read and write accesses.

A complete system can be developed, one that implements the lower layers in FPGA logic and the upper layers as an application on the ARM processor (Figure 4).

 Figure 4: BSDK embedded application architecture

Figure 4: BSDK embedded application architecture

Nutaq provides an External API (EAPI) with the ZeptoSDR to configure the Radio420 from a host computer.

To enable the EAPI, a central command engine (CCE) runs on the Zynq ARM processor. The CCE receives commands from the host computer and executes the corresponding API functions. To enable the streaming of data between the FPGA and host computer, the Zynq runs an RTDEx Server application. All it does is data transfer between the RTDEx device and a TCP socket. This enables a host computer to exchange data with the FPGA logic.

In this kind of application, no processing is done by the ARM processor. The ARM processor is only used as a bridge for commands and data transfers between the programmable logic and a host computer.

A complete system, implementing lower layers in FPGA logic and the upper layers as a program running on the host computer, can be developed (Figure 5).

Figure 5: BSDK remote application architecture

Figure 5: BSDK remote application architecture

Developing an embedded application on the Zynq processor that uses a TCP socket and the RTDEx device lets you use a hybrid architecture. For example, the lower layers can be developed on the FPGA logic, mid-layers on the Zynq processor, and upper layers on the host computer.

Conclusion

With all the different processing elements available on the ZeptoSDR, developers can implement a wide range of applications depending of the latency specifications, the required processing power, and time-to-market constraints. The ZeptoSDR reference designs and API make it much easier to understand the hardware and to speed up application development. With the ZeptoSDR, new SDR applications that take advantage of the Zynq SoC are just waiting to be created.