In this post we present ”Using FPGAs In Multichannel DAQ Systems”. The content of this blog is taken directly from our paper which you can download here.

 

The electronic hardware of a multichannel DAQ system which will be used for applications such as small animal imaging (PET, MicroPET, MRI), linear accelerator BPM/ LLRF, and radio astronomy requires specialized equipment having very high-end capabilities. The system must interface with a potentially large number of sensors, and it must perform complex and sophisticated processing on the acquired data. Re-programmability is also key here in order to try various possible algorithms. Not only that, but to make sense from an investment perspective, it also must be cost effective.

Field Programmable Gate Arrays (FPGAs) can significantly reduce the complexity and cost of designing and creating sophisticated multichannel DAQ systems. Let’s take a look at how they can do this. In addition, they provide the required flexibility which allows for various algorithms to be explored in the R&D phase, and firmware upgrades to be performed once the system is deployed.

FPGAs can present massive benefits through parallel processing

Most conventional processors such as general purpose processors (GPPs), and digital signal processors (DSPs) typically have a limited number of computing resources such as ALUs (arithmetic logic unit), CPUs (central processing units), memory blocks, internal data paths, input/output (I/O) ports, and so on. These processors must perform their operations sequentially because they can operate on only one set of data at a time.

On the other hand, FPGAs can offer thousands of building blocks such as ALUs, extremely large quantities of general-purpose digital logic and internal data paths, and large numbers of memory blocks and I/O ports. All of them can be interconnected and made to operate simultaneously in a parallel manner.

Take for example a simple processing algorithm performed in a hypothetical multichannel DAQ system. The algorithm involves three parallel computing sequences that combine to produce a final result, as shown in the following figure:

In a conventional computing system, each sub-process is implemented as a separate software function, and the process flow looks like the following:

In this case, everything is executed as a sequence of functions, and each function is itself executed as a sequence of instructions. As can be inferred from this, the more complex the algorithm is, the longer the sequence of processing instructions becomes, which could eventually lead to an overload of the processing capabilities of the system.

In the case of an FPGA, each process is implemented as a combination of elementary FPGA building blocks, resulting in a process flow that looks like the following:

You can see that the FPGA implementation is an almost exact replica of the original algorithm. The FPGA blocks represent the same combination of parallel and sequential operations of the algorithm and, internally, each block can also be implemented as a combination of parallel and sequential sub-computations. In contrast to a sequential processor, which could become overloaded by the complexity of the algorithm, an FPGA can adapt by allocating additional computing resources as needed (up to the limit of the FPGA device itself, or compatible auxiliary devices). Comparing the two diagrams, we can also clearly see the FPGA allows a low-latency solution for implementing the algorithm.

A typical view of a multichannel DAQ system

A multichannel DAQ system must process data that is inherently parallel. Analog data from arrays of sensors must be synchronously digitized and processed based on a common timing reference. Processing data from parallel sensors (data channels) using conventional sequential processors (such as DSPs or GPPs) may involve complicated and inefficient manipulations of data that can potentially overload the computing capabilities of the system.

The following figure shows an example of a traditional system:

In this system, the data goes through the following processing steps:

1. Analog data from sensors is digitized by analog-to-digital converters (ADCs).
2. Special interfaces extract the data from the ADCs.
3. Parallel data from each of the ADCs is placed in a sequential queue so that it can be acquired by the processor through its single input port.
4. Each data element is taken from the queue one by one and sent to a sequence of computing processes (processes 1 to 6 in the example). This process is then sequentially repeated for all data channels.
5. Additional steps are performed to make decisions based on the processing of all the channels and an output is generated.

In contrast to conventional processors, FPGAs are not limited by the number of input (or output) ports and they can process as many channels in parallel as required. FPGAs can even directly integrate the interface to the ADCs (even in conventional sequential computing machines, the ADC interface and queuing mechanism would most likely be implemented in an FPGA). Many computing processes (processes 1 to 6 in the example) can also be performed to a certain extent in parallel. The result is shown in the following example:

This provides an implementation that is much simpler, more efficient and more representative of the intended processing structure of the application.

 

The content of this blog is taken directly from our paper which you can download here.