If we look at the ZeptoSDR and PicoSDR faceplates, they each have the following ports: Ref In, Ref Out, RX, TX and PPS In (each connector is doubled in 2×2 MIMO configuration).

The purpose of the RX and TX ports is straight-forward – they are used to plug in the transmit and receive antennas. To understand the uses of the Ref Out and Ref In ports, we need to understand the clock management circuitry of the FMC radio card in both systems.

The FMC radio can be divided into three main blocks: RFIC (LMS6002D), RF path (includes the filter banks and LNAs), and clock/reference management.

The TX and RX ports are connected to the RF path block, which in turn is connected to the LMS6002D chip. The Ref In and Ref Out ports are connected to the clock management section. The most important part of the clock management section is the PLL, which uses 30.72 MHz or the Ref In input clock as a reference to generate the required clocks for the LMS6002D chip.

There is also a PLL inside the RFIC that generates the actual local oscillators for RF transmission and reception. Three clocks are sent to it: the ADC clock, the DAC clock, and the 30.72 MHz clock.

The ADC/DAC clock is also sent to the FPGA, which means all the data flow between the ADC/DAC and the FPGA can be directly synchronized in one system. However, when you have more than one FMC radio in a system (for example, in PicoSDR 2×2, 4×4 or two 4×4 systems), the 30.72 MHz clock references for each FMC radio will definitely be different. The exact frequency of each clock differs when they get out of the factory. Their frequency may also drift over time and change depending on the temperature.

This is where the Ref In and Ref Out ports become very useful. You can use the 30.72 MHz reference clock from one FMC radio as a reference for the others by daisy chaining it between the boards. This guarantees that each PLL will use the exact same reference frequency, which in turn will make the PLLs generate the same frequencies.

Note however, that since a PLL device has a variable locking time, the generated clocks will not be synchronized in phase. Phase synchronization will be covered in Part 2 of this series.