In a previous post, we presented an overview of a PET scanner’s operation and key components, and we presented some of the limitations of the common technologies used in PET design. Universities, being important research institutions in science and engineering, are often the place where new technologies that arrive to market are born, developed, tested and evaluated.

In this second post, we examine how Sogang University has looked to the future by replacing common PET scanner components with new technologies, and by integrating real-time digital signal processing units in the system. We also present some of the choices made by the Sogang team to reduce the cost and development duration of their brain PET scanner.

 

Coincidence Processing Unit: CFD & TDC vs. Free-running ADC- & FPGA-based Signal Processing

 

In the previous post, we discussed that the constant low and high thresholds of constant factor discrimination (CFD) in conventional PET systems were an important limitation in discerning between events caused by scattered photons as opposed to non-scattered photons. The main issue is the resolution of the sensors doesn’t allow accurate photons discrimination since many scattered annihilation photons have energy close to the expected 511 keV of non-scattered photons.

Furthermore, we learned that the conventional time-to-digital converter (TDC) uses a constant coincidence detection window that has an important impact on the image resolution since, again, the chosen window could increase the rejection of positive coincidence events or, conversely, the erroneous consideration of random coincidence events.

In Sogang University’s “digital timing method” implementation, they completely removed these two parts from the system and replaced them with eighteen 64:1 position decoder circuits (PDCs) connected to three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards

[1].

 Simplified diagram of Sogang’s digital timing method implementation

Figure 1 : Simplified diagram of Sogang’s digital timing method implementation

 

In short, each time the Position Decoder Circuit receives the signal from one of the 64 GAPD channels, it transfers the pulse with the corresponding digital map address of the GAPD sensor to the free-running ADCs- and FPGA. The pulse is sent to the analog acquisition input, and the map address is communicated to the FPGA by the FPDP/GPIO port of the acquisition device. With this system configuration, the brain PET has all the data to analyze the arrival timing, energy level, and position of each gamma ray signal without using constant discrimination variables such as in CFD and TDC. Actually, the parallel signal processing of these characteristics was carried out directly by an algorithm implemented in the FPGA, the results of which were transferred to the computer via the compact PCI (cPCI) interface [1].

For the performance evaluation and test results of the brain PET, please refer to the article “Free-running ADC- and FPGA-based signal processing method for brain PET” from Sogang University [1].

 

Speeding Up Design Implementation While Reducing Cost and Complexity

 

As described in the article from Sogang University, the key elements that reduced the cost, complexity and development duration of their prototype were:

  • the digital processing approach based on FPGA
  • the use of off-the-shelf DAQ cards
  • the use of their associated development toolkits

 

FPGA Digital Processing

 

A key feature in this implementation is the digital processing by the FPGA. As discussed in the blog post Optimizing the Number of Analog-To-Digital Converters in Small Animal Imaging (SAI) Systems, FPGA is capable of analyzing signals from a multitude of sensors simultaneously and in parallel, which is often necessary in complex applications. I strongly recommend reading this blog for additional information about this interesting method in multichannel acquisition systems.

Furthermore, compared to microcontroller and DSP, FPGAs contain a huge number of digital circuits (called arithmetic logic units or ALU) that are capable of performing integer arithmetic and logical operations, which is optimal, as just mentioned, for parallel processing. More interestingly, FPGAs are designed with pre-built digital signal processing blocks such as FFT, DDS, filters, trigonometric functions, and so on, permitting fast implementation. Learn more about FPGA processing power in the post The Advantages of Using FPGAs in High Speed, High Density Data Acquisition Systems.

 

Commercial-Off-The-Shelf DAQ Cards: 3x Nutaq VHS-ADC

 

As we now know, Sogang University used three DAQ cards to develop their brain PET prototype and demonstrate the capabilities of this new technological approach to designing PET systems. More precisely, these three off-the-shelf cards were Nutaq VHS-ADC cards. These development platform cards are specifically designed to fulfill the needs of any type of application requiring multichannel data acquisition, digital processing, data synchronisation, and more. Check out the VHS-ADC web page for more information.

Commercial-Off-the-shelf (COTS) equipment is noteworthy in reducing development effort and often cost as well. Since they’re already integrated, debugged and ready to be adapted to any custom application out of the box, they can provide significant benefits. While these COTS systems often require some external components to interface with your application, you usually get great support from the manufacturer to help you achieve your goals.

Nutaq VHS-ADC

Figure 2: Nutaq VHS-ADC

 

Model-Based Design Kit (MBDK)

 

To accelerate the project implementation, Sogang University developed their FPGA application using the model-based design kit (MBDK) provided with Nutaq’s equipment.

In short, the FPGA application was developed directly using the graphical programming interface that eased the implementation of the algorithms, the data management between the modules or equipment, and the control of the equipment.

FPGA Image Development Using Xilinx and Nutaq

Figure 3: FPGA Image Development Using Xilinx and Nutaq

 

By leveraging the robust Simulink® library from MathWorks®, including configurable processing blocks that can be simply dragged and dropped in the project, the Sogang team was easily able to create, simulate, test and debug the FPGA application.

Digital processing blocks such as digital time pick-off, baseline restoration, and pile-up rejection or recovery were readily implemented in the FPGA to improve PET system performance. An image of the team’s design in Simulink is provided on page 4 of their article [1].

When their application was ready for that critical moment of testing it in their system, the System Generator for DSP™ from Xilinx® generated the FPGA binary file (also called bitstream) used to program the FPGA, directly from the Simulink project.

The blog post Using a Model-Based Approach to Ease the Implementations of FPGA Data Acquisition Systems provides an interesting example explaining how to create your FPGA application using the MBDK. I also suggest reading more about MDBK here.

 

Sogang’s Success

 

In this second post, we covered how Sogang successfully developed a brain PET prototype using free-running ADCs and FPGA as a coincidence processing unit.

In addition, the integration of digital signal processing in PET design broke new barriers in the digital world, where limits are pushed forward every day. The PET scanner will then continue to be improved with better and better DAQ systems and more efficient detection algorithms.

Finally, we discovered how the cost and the development duration of the system were reduced using off-the-shelf DAQ systems (including ADCs and FPGAs) and their associated graphical programming development kits–in particular, Nutaq’s MBDK.

References

1. Hu, Wei, et al. 2011. “Free-running ADC-and FPGA-based signal processing method for brain PET using GAPD arrays.” Nuclear Instruments and Methods in Physics Research A. doi:10.1016/j.nima.2011.05.053