In this post we present ”Offloading GNU Radio Processing with FPGA Logic”. The content of this blog is taken directly from our paper which you can download here.

 

GNU Radio is an open source software toolkit that accelerates the development of software defined radio (SDR) thanks to the signal processing blocks it provides. GNU Radio digital signal processing blocks run on the computer CPU. When many mathematical operations need to be performed (such as addition, multiplication, filtering, and so on) and when the data rate is high, the computer may be unable to perform all these operations at the speed that’s required.

In cases such as these, the developer may seek to offload the CPU processing onto an FPGA, such as the Xilinx Virtex-6 (which is available on Nutaq’s PicoSDR solution). While FPGA algorithm development is often slow and painful to debug, developers can choose to work in a model-based environment (see Nutaq’s Model-Based Design Kit) which enables faster development while providing easy-to-use simulations by taking advantage of the Simulink® environment from MathWorks®. It also allows designers who aren’t familiar with FPGA to quickly understand the signal processing flow that will be implemented inside the FPGA. No VHDL or Verilog knowledge is required.

In this article, we’ll implement a digital up-converter (DUC) inside the FPGA. This will decrease both the processing done in GNU Radio as well as the communication bandwidth required to transfer the data between the PC and the FPGA platform.

A Basic Nutaq Model-Based Design Kit (MBDK) Model

Figure 1: Basic MBDK Model

The figure above shows a simple MBDK example using Nutaq’s Radio420X and High-Speed Real-Time Data Exchange (RTDEx) IP blocks. This example connects the Radio420X ADC and DAC interfaces to the RTDEx TX and RX channels. Because the Radio420X interfaces use interleaved IQ data, there is either an IQ mux or an IQ demux block between each RTDEx and Radio420X block to convert interleaved IQ data to two independent streams, and vice versa.

A generated bitstream of this model can easily be used in GNU Radio to stream data between the PC and the Perseus 601X card, which houses the Virtex-6 in the PicoSDR system. In this example, we’ll modify this simple model to include some real-time signal processing in the FPGA. We’ll add a DUC between the RTDEx RX blocks and the Radio420X DAC interface to decrease both the RTDEx data rate required as well as the processing done in GNU Radio.

The Radio420X digital interface can run at up to 80 MHz. At this rate, GNU Radio will need to generate and process 80 megasamples each second and send them through the RTDEx physical layer. Even if your PC can handle this data rate for your given signal processing application in GNU Radio, the physical layer can have a hard time keeping up with this throughput. Assuming 2 bytes per sample, this corresponds to 1.2 Gbps in transmission and in reception. This bit rate exceeds the gigabit Ethernet capacity, and we have only one Radio420X in SISO configuration in our model. In our example, because interpolation will be done inside the FPGA, the data rate will be slower and the Radio420X will be able to run at full speed.

Creating a DUC in the Transmission Path

Figure 2: MBDK model including a DUC

The figure above shows the MBDK model including a DUC. Upsampling and frequency shifting blocks have been added between the RTDEx RX blocks and the IQ Mux. These new blocks are configured by custom registers and 1. Custom register 0 drives the upsampling rate and custom register 1 determines the DDS (direct digital synthesizer) frequency used to shift the upsampled signal.

 

The content of this blog is taken directly from our whitepaper which you can download here.