In a previous blog post, I mentioned the importance of having symbol timing recovery in digital I/Q receivers and reviewed some popular recovery methods, including late-early
Theory behind the Gardner method
Figure 1: Gardner timing error computation
The Gardner timing recovery algorithm requires two samples per symbol and knowledge of the previous symbol timing in order to estimate the timing error for the current symbol, as shown in Figure 1. The timing error computation for either the I or Q rail is computed as follows:
where T is symbol duration. Once the timing error is computed, the Gardner timing adjustment algorithm is performed:
· If e = 0 , no timing adjustment is required for the next symbol
· If e < 0, a timing advance is required for the next symbol
· If e > 0, a timing delay is required for the next symbol
Implementation in System Generator
Implementation of the Gardner symbol timing recovery is illustrated in Figure 2. A 4-QAM modulation scheme is used in the baseband modulator, followed by a translation to an intermediate frequency (IF) of 8 MHz at a higher sample rate. At the receiver, the digitalized samples from the ADAC250 analog-digital converter (ADC) module are IF down-converted to baseband before being fed to the timing recovery circuit.
Figure 2: Gardner timing recovery System Generator model
Details of the timing recovery circuit are shown in Figure 3. In the figure, the input symbols, which have four samples per symbol, are averaged in order to mitigate noise and have a triangular shape per symbol as shown in Figure 4before the Gardner timing error is estimated. It is also necessary to average the timing error before the loop filer in order to generate the timing control word (TCW) for the symbol sampler circuit. The closed-loop symbol sampler circuit is sometimes called the delay locked loop (DLL) circuit. The symbol sampler gates the x[nT], x[(n-1)T], and x[nT – T/2] samples by the comparing of a 2-bit free-running counter in the symbol sampler with the feedback TCW from the loop filter. As a result, the incoming symbol sampling time will be advanced or delayed by one sample at a time. Once the timing control loop locks to perfect timing (maximum opened eye-diagram), there will be no timing adjustments (the timing loop keeps the last timing estimated value) for the incoming symbols.
Figure 3: Gardner symbol timing recovery loop
Figure 4: Moving average input over 4 samples
Figure 5 shows the simulation of the timing recovery locked-loop of the I rail. Timing recovery for Q rail consists simply of sharing the timing information from the I rail since I and Q rails are synchronously obtained from the IF digital down-converter that connects to a single ADC channel (the ADAC250 module ). If the I and Q rails are obtained from two independent ADC channels, independent timing recovery circuit per I/Q rails would be necessary.
Figure 5: Gardner timing recovery loop simulation
In this blog post, we looked at simulation of Gardner symbol timing recovery for I/Q demodulator in System Generator. A simple closed-loop timing control that adjusts the symbol sampler to either advance or delay in time the incoming symbols to get the perfect timing was also illustrated.
Bernard Sklar, Digital Communications: Fundamentals and Applications: Prentice-Hal, 1988. [Online]. Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J., Prentice-Hall, 1988.
F. M Gardner, "A BPSK/QPSK Timing-Error Detector for Sampled Receivers," IEEE Transactions on Communications, vol. COM-34, no. 5, pp. 423-429, 1986.
K. H., and M. S. Muller Mueller, "Timing Recovery in Digital Synchronous Data Receivers," IEEE Transactions on Communications, vol. COM-24, pp. 516-531, 1976.
Nutaq Inc. (2014) ADAC250. [Online]. https://www.nutaq.com/products/adac250