This blog post is the first in a series on how use a model-based design approach when designing and implementing your field-programmable gate array (FPGA). Each step, from FPGA bitstream generation to interfacing with an external computer for control and real-time data transfer, will be explained. The goal of this series is to demonstrate the development process of Nutaq’s Model-Based Design Kit (MBDK) so you can get comfortable in the design environment as soon as possible. This will be achieved with simple tutorials showing how to perform a specific task inside the FPGA logic.
Basically, the MBDK is a custom compilation flow on top of Xilinx System Generator. MBDK enables users to develop all their algorithms inside the model-based environment of System Generator and generate a ready-to-use bitstream in one click. To achieve this, the MBDK takes charge of all the hardware interfaces on the FPGA board and provides access to their functionalities. It also provides user-friendly interfaces inside System Generator. For example, data transfer over Gigabit Ethernet, PCIe or Aurora interfaces is supported as well as data recording and playback with DDR3 memory. A wide variety of FPGA mezzanine cards (FMCs) are also supported.
Figure 1: Custom register blocks
In this first tutorial, only the custom register (CR) functionality of the MBDK will be used. The custom register blocks enable an application to write or read register values inside the FPGA. These registers have no pre-defined task and can be used inside a user’s design to provide control and status interfaces for the FPGA logic that are accessible by an external application.
In this tutorial, an adder of two 32-bit registers as well as a multiplier will be implemented inside the FPGA. An application running on an external computer will be able to set the values of the two input registers as well as retrieve the adder and the multiplier results.
First, MATLAB and Nutaq’s MBDK must be installed on the computer.
To launch System Generator, click the Windows Start menu. In the Xilinx ISE Design Suite folder, right-click on System Generator and select “Run as administrator”. This launches MATLAB and ensures you have the necessary system privileges required by Nutaq’s MBDK.
Next, select your working directory by modifying the MATLAB’s “Current Folder”.
Figure 2: Creating an MBDK empty project
Inside the Simulink Library Browser window, click on the New model button. In Simulink Library Browser, click on the Xilinx Blockset library and drag the System Generator block into your empty model. Also, open the Nutaq Perseus 601x Blockset library and drag the Perseus 601x block into your model.
Figure 3: Default MBDK project
In your model, double-click on the System Generator block. For the Compilation parameter, select Hardware Co-Simulation > Nutaq > Perseus601x. Next, select your FPGA type under the Part parameter.
Figure 4: System Generator block
Double-click on the Perseus 601x block and select 100 MHz for the Clock source parameter. This makes your MBDK logic run at 100 MHz from an internal clock on the Perseus601X board. Select GIGe 0 as the CCE interface. This enables you to access your Perseus601X over a Gigabit Ethernet connection with an external computer.
Figure 5: Perseus601X block
These two blocks (System Generator and Perseus601X) are always required to generate an FPGA bitstream from the MBDK.
Once they are added to the model, other Nutaq and Xilinx blocks can be added, letting you choose which hardware interfaces of the Perseus601X to use when implementing your algorithm. In the next post in this series, we’ll look at adding the interfaces that will be used to generate the arithmetic operators controlled by the custom registers inside the FPGA.