Digital pulse processing is the process of numerically analyzing pulses of physical attributes. This processing is the key to a wide range of applications. The processing differs depending on the purpose of the application. For example:

  • In nuclear medical imaging, positron emission tomography (PET) systems detect pairs of gamma rays emitted indirectly by a tracer that was previously introduced into the body of the patient. The system detects and associates pairs of digital pulses to determine their origins. Three-dimensional images of tracer concentration within the body can then be constructed.
  • Dual-energy X-ray Absorptiometry (DXA ) is widely used to diagnose and follow osteoporosis. This technique consists of alternating between different energy levels of X-rays. The resulting energy images are then compared, providing information about the bone density.
  • Baggage and cargo scanning uses digital pulse processing techniques such as Z-scan and Z-spectroscopy. The Z-scan technique (also known as statistical count-rate analysis) detects and measures the variance of X-ray pulses, which depends on the average atomic number (Z) of the sample. Z-spectroscopy measures the full energy spectrum of the received X-rays pulses, which also provides information about Z.

This blog post summarizes a preliminary study of an FPGA-based implementation of the Z-spectroscopy algorithm used in baggage and cargo scanning.

 

Z-spectroscopy Algorithm Review

 

The choice of the X-ray source combined with the detectors affects the pulse shape (energy, rate, and pulse width). They are the main factors that determine the required ADC sampling frequency and resolution. The digital processing portion of the Z-spectroscopy algorithm comes right after the ADCs and can be divided into the following sub-tasks:

  • DC-offset removing: The DC offset component is generally removed from the digital samples.
  • Filtering: Filtering might be required in order to remove some noise and might simplify the pulse detection algorithm.
  • Pulse detection: This algorithm detects peaks in the samples. Different parameters like minimum peak value and pulse duration are used to avoid false detection. For better results, care must also be taken regarding pulse pileup (superposition of two or more pulses).
  • Histogram (pulse aggregation): The whole pulse energy range is divided into segments. The division might be linear or of any desired distribution. The number of segments depends on the required resolution. The maximum energy level of each pulse (peak) is measured and counted according to its associated segment. The resulting output is a histogram representing the energy distribution of the X-rays.
  • Histograms analysis – image synthesis: Finally, the histograms are analyzed by a PC-based system to generate an image of the object being scanned. This information might also be combined with results from different detectors or other scanning techniques.

 

Implementation on the Perseus 601x platform

 

For this implementation, we need a minimum sampling frequency of 250 MHz, since the target system is a combination of X-ray source and detector producing an average X-ray rate of 30 MHz, or about one pulse every 30 nsec. We’ll be using FPGA-based system for algorithm evaluation, along with a connection to a host PC.

 

Hardware Setup

 

The selected setup is a Perseus/ADAC250 platform, as shown in the photo below.

Perseus ADAC250 platform setup

Figure 1: Components used in the Z-spectroscopy algorithm implementation

The main components are:

  • MicroTCA chassis
  • Perseus 6010 motherboard
  • ADAC250 FMC card
  • A pair of DAC-ADC loopback cables
  • Gigabit Ethernet cable connected to a host computer

 

Z-spectroscopy Algorithm Implementation

 

The following block diagram illustrates the Z-spectroscopy algorithm implementation. This implementation uses an input signal sampled at 250 MHz.

Z-spectroscopy algorithm implementation block diagramFigure 2: Z-spectroscopy algorithm implementation

 

The System Generator for DSP™ from Xilinx® is used to implement the algorithm, except for the Ethernet interface. System Generator is a tool for FPGA design implementation that is fully integrated with both MATLAB® from MathWorks® and the Perseus 601x platform. As an example, the figure below shows a model that performs the moving average, having a configurable length of 2, 4, 8 or 16 samples.

 

model that performs the moving average using System Generator FPGA design implementation

 

Algorithm Validation

 

The FPGA algorithm implementation was first validated in the MATLAB environment, using pre-recorded data from a real system. It was then tested on hardware by substituting the ADC values with data from the test bench. Finally, it was tested using the DAC to generate (emulate) the X-ray pulses using the same pre-recorded data.

Resource usage

The following table summarizes the resources used for each sub-processing block. The total usage corresponds to less than 1% of the Virtex-6 LX240 FPGA’s resources.

resources used for each sub-processing block table

 

What’s next?

 

We have successfully implemented a preliminary FPGA-based application of the Z-spectroscopy algorithm used in baggage and cargo scanning on a Perseus 601x platform. Given that the resources are not a limiting factor, it would be interesting to implement a multi-channel scanning system on one FPGA using the MI250 board. Nevertheless, since cargo scanning systems require a very large number of sensors (sometimes in the thousands), there are two possible approaches we can take from this point on: use an FPGA as big as possible and interface all the sensors to it, or distribute the various processing elements throughout the system.

This first analysis shows that a Virtex-6 LX240 could potentially accommodate up to 100 channels. In the case of cargo scanners, which are very large devices, interfacing such a high number of channels on the same processing platform is likely to cause problems. The long distances sensor signals have to travel to get to the board and the limited number of FPGA IOs restricts the number of ADC interfaces per FPGA. In this specific case, very high density FPGAs, such as the Virtex®-6 and Virtex®-7 families from Xilinx, are then inefficient. The final product is likely to make use of smaller FPGA devices such as the Xilinx Spartan®-6 and ARTIX™-7 families, distributed all along the system.

 

References

  1. Langeveld, Willy, Tsahi Gozani, Michael King, John Stevenson, Dan Strellis. 2011. “Neutron-based Material Categorization System for the Rapiscan Eagle MAX.” International Workshop on Fast Neutron Detectors and Applications. Ein Gedi, Israel. 8 November 2011. http://www.fnda2011.de/pdf/06-04.pdf