In this series:
- Xilinx System Generator tips and tricks – Part 2: HDL code reusability
- Xilinx System Generator tips and tricks – Part 3: Using MATLAB M-function for easy state machine coding
- Xilinx System Generator tips and tricks – Part 4: Understanding timing issues
- Xilinx System Generator tips and tricks – Part 5: Simple methods to fix timing issues within System Generator
- Xilinx System Generator tips and tricks – Part 6: Timing issues outside the box.
I’ve been working with Xilinx System Generator for DSP for about ten years and have designed many different applications with it, including GSM/EDGE layer 1, direction finding, and pulse processing applications. These applications may seem very different at first glance, but at their core they share similar functionalities, all of which can be grouped together as digital signal processing (DSP) functions – something that System Generator models very well.
I’ve also been involved in different projects in a consultant role, supporting customers and helping them develop their own applications with System Generator. Lots of universities and industry R&D teams have a deep knowledge of the algorithms they want to design. But if their application cannot be implemented with standard software languages and they want to prototype and implement their algorithms on faster devices like FPGAs, they sometimes hit a wall.
Xilinx System Generator is an easier way to implement DSP algorithms in FPGAs than HDL, and a natural path for algorithms already designed in MATLAB. But like any language, System Generator has its own challenges. This blog series is mainly for people with some basic knowledge of System Generator or for people who are just starting to learn. Even if I still have a lot to learn myself, I think sharing my experiences and pointing out the common mistakes I see will be useful for others.
For the first part of this series, let’s introduce System Generator and show an example highlighting some of its main benefits.
An overview of Xilinx System Generator
System Generator is a high-level tool developed by Xilinx and is fully integrated in MATLAB Simulink for designing high-performance DSP systems targeting FPGAs. The Xilinx/MATLAB Simulink blockset contains a wide range of primitive functions and sophisticated signal processing functions. These let you to develop your own algorithms easily and greatly benefit from the MATLAB environment during the design and test phases.
The main highlights are:
- DSP modeling – The Xilinx blockset contains all necessary functions for modeling:
- Signal processing (e.g. CORDIC, CIC and FIR filters, FFTs, Viterbi decoder)
- Arithmetic and logic (e.g. multiplier, adder, comparator, shift)
- Memories (e.g. registers, FIFO, ROM)
Figure 1 presents some of the cores available in the Xilinx blockset.
Figure 1: Xilinx blockset
- Bit and cycle-accurate floating and fixed-point implementation – System Generator guaranties that the output results obtained during the design phase within Simulink are the same as the ones generated by the corresponding FPGA implementation.
- Easy path to FPGA – You can generate HDL code directly from Simulink.
- Hardware co-simulation – More than 400 pages long, the Xilinx System Generator for DSP User Guide is a good reference document. But for people who want to get a good feeling about it in less time, you can find few good tutorials on the web.
A System Generator example
Figure 2 shows an example included with the default System Generator installation, version 13.4. It corresponds to a GSM digital down converter (DDC). The model takes a complex wideband signal as input, mixes it to convert the desired channel to baseband, and then filters and downsamples the signal to reduce it to the bit rate.
Figure 2: GSM DDC example
Let’s discuss a few of the benefits demonstrated by this example:
- Stimulus generation – Since System Generator is integrated in Simulink, the stimulus can be generated using Simulink blocks. In fact, any waveform can be generated using the power of MATLAB and used in the Simulink model via From Workspace blocks.
- Analysis – All outcomes and intermediate results can be recuperated and analyzed within Simulink (using scopes and spectral analyzers, for example) and can also be saved in the workspace and analyzed later within MATLAB.
- DSP design – Figure 3 and Figure 4 show the DDC design. Even if the computation is quite complex, the model stays relatively simple. The complete design is a combination of Xilinx blocks. The mixer is made of multipliers and one DDS, while the filtering is composed of CIC and MAC filters.
Figure 3: DDC logic
Figure 4: Mixer logic
- Easy path to FPGA – Figure 5 shows the System Generator block menu. In few clicks, you can generate the associated HDL code or directly generate a bitstream.
Figuer 5: System Generator block
Xilinx System Generator is well-suited for developing DSP applications. Not only does the Xilinx blockset contains many different DSP cores, the designer benefits from the MATLAB environment when generating stimulus and analyzing the outcomes of his or her model.
But while System Generator is faster and simpler than HDL to target FPGA, it still has its own share of difficulties. In my upcoming blog posts, I share my experiences and discuss common mistakes that I’ve encountered