During the RX DC offset calibration, the FPGA averages the signal received to calibrate the DC offset. Typically, when an error occurs, it is because the acquired signal saturates at the ADC and is clipped when sampled in the FPGA. Reduce the power inputted to the Radio 420 RX or reduce the RX gain to avoid signal saturati
When running a Radio 420x example, I obtain an RX DC offset calibration failure. What is causing the failure and how can I solve it?