In this series:
- Rapid DSP application development for Xilinx FPGA platforms – Part 1
- Rapid DSP application development for Xilinx FPGA platforms – Part 2
- Rapid DSP application development for Xilinx FPGA platforms – Part 4
In Part 2 of this blog series, we imported a pcore generated from a System Generator model into a Xilinx FPGA development platform (Nutaq’s ZeptoSDR). Like I mentioned at the end of the post, if you are using System Generator 14.5 or older, you will encounter a problem regarding the direction of the signal vector. If you don’t have this problem, you can skip directly to the ‘Port connection’ section later in this post.
Bug fix for System Generator 14.5 or older
To solve this issue, you need to modify two files: the MPD file and the cnt_sysgen_axiw.vhd of your pcore. You can access both of these files directly by right-clicking on the cnt_sysgen_axiw_0 core.
Let’s start with the MPD file:
Here’s what you should see:
There are obviously many ports defined in this file (the previously performed pcore generation also created code to use it on an AXI bus). We won’t use this functionality, however, so the only port relevant to us is gateway_out. The output port vector is defined as