In this series:

In the previous blog post on Xilinx System Generator tips and tricks

[1], my colleague highlighted one of the biggest advantages of System Generator: the rapid targeting of digital signal processing (DSP) algorithms to field-programmable gate array (FPGA) devices without using a hardware description language (HDL). In Part 2 of this series, I describe another interesting advantage of System Generator: creating a custom block in MATLAB/Simulink environment by reusing HDL code. System Generator provides a primitive called Black Box that allows FPGA designers to reuse their existing HDL codes within a self-contained “black box” block.

In this post I show how to use the black box functionality with an example that reuses existing VHDL code for a Gaussian random number generator as a System Generator block for a white noise generator design.

Naming convention

Figure 1: Existing VHDL code

Figure 1: Existing VHDL code

Figure 1 shows a hierarchical view of Gaussian random number generator project. The top-level entity references several entities in different VHDL files.  The top-level VHDL file must meet the signal name convention of System Generator. Clock and chip enable ports are required and must be named “clk” and “ce”, respectively, as shown in Figure 2, while the other ports are user defined.

Figure 2: Top-level port naming convention

Figure 2: Top-level port naming convention

Creating a custom block

Figure 3 shows the location of the Black Box element in the Xilinx Blockset library. We need to point it to the top-level VHDL file when it’s dragged into the user project. System Generator will automatically create a configuration file of the given Black Box (gauss_toplevel_config.m in this example).

Figure 3: Locate Black Box in library

Figure 3: Locate Black Box in library

Black Box configuration

It is important to add the VHDL files that are referenced in the top-level entity to the Black Box configuration file. The highest level (top) in the HDL hierarchical will be the last VHDL file and the lowest level will be the first VHDL file in the Black Box configuration file. Failing to put the VHDL files in the right order will cause errors during compilation and simulation.

Figure 4: Add VHDL sources to Black Box configuration

Figure 4: Add VHDL sources to Black Box configuration

In order to see the white noise generator simulation result, the ISE Simulator option must be selected in the Black Box property dialog box, as shown in Figure 5.

Figure 5: Enable simulation option

Figure 5: Enable simulation option

Interface with other System Generator blocks

By default, the output ports with std_logic and std_logic_vector data types at the top-level entity are translated into the UFix data type in the MATLAB/Simulink environment. Therefore, it is necessary to change them to right data types depending on design requirements.  In this example, I changed the valid output port of type std_logic into the Bool data type and the noise output port of type std_logic_vector into the Fix_10_6 2’s compliment data type, as shown in Figure 6.

Figure 6: Change output data types

Figure 6: Change output data types

A complete example of white noise generator model is shown in Figure 7. In this figure, the reset, run and output noise gain ports are interfaced with custom register (CR) of the Perseus 601x platform [2] to enable you to control the design. The noise output of the Black Box is adjustable via a simple multiplication with a constant from CR interface. Multiplication noise results can be observed in both digital domain and analog domain via the ChipScope interface and the analog output of ADAC250 module [3]

Figure 7: Gaussian white noise generator model

Figure 7: Gaussian white noise generator model

Hardware testbed

The ADAC250 module stacks on top of the Perseus 601x platform via an FPGA mezzanine card (FMC) connector inside the PicoSDR 2×2 chassis [4], as shown in Figure 8  (front faceplate has been removed). The ADAC250 provides a clock source for the design and performs high-performance digital-analog conversion of 16-bit digital white noise samples.

Figure 8: White noise generator hardware setup

Figure 8: White noise generator hardware setup

The implementation results of the example design digital and analog domains can be seen in Figure 9, and Figure 10, respectively.

Figure 9: 16-bit digital white noise samples captured via ChipScope

Figure 9: 16-bit digital white noise samples captured via ChipScope

Figure 10: Analog white noise at DAC output captured at oscilloscope

Figure 10: Analog white noise at DAC output captured at oscilloscope

Conclusion

This blog post described an approach that allows FPGA designers to quickly integrate existing algorithms in HDL code into the MATLAB/Simulink model-based design environment using System Generator’s Black box. To demonstrate code reusability, the VHDL code for a Gaussian random number generator was used in a model-based white noise generator.

References

[1] David Quinn. (2014) Xilinx System Generator tips and tricks – Part 1: An introduction. [Online]. http://www.nutaq.com/blog/xilinx-system-generator-tips-and-tricks-%E2%80%93-part-1-introduction

[2] Nutaq Inc. (2014) Perseus 601X. [Online]. http://www.nutaq.com/products/perseus-601x

[3] Nutaq Inc. (2014) ADAC250. [Online]. http://www.nutaq.com/products/adac250

[4] Nutaq Inc. (2014) PicoSDR. [Online]. http://www.nutaq.com/products/picosdr