Field-programmable gate array (FPGA) boards are normally used to implement low-level radio frequency (LLRF) digital control loops and beam positioning algorithms. Nutaq’s Perseus 601x advanced mezzanine card (AMC), for example, is based on the Virtex-6 FPGA and offers high-performance, high-bandwidth, low-latency processing. Its MicroTCA software tools are highly suitable for the development of control algorithms for linacs and other high-energy physics applications.
Figure 1: Perseus601x block schematic
High-pin-count (HPC) FGPA mezzanine card (FMC) sites enable the addition of high-speed and high-channel-count analog or digital input/output (I/O) cards to the FPGA carrier. Observed trends in the last few years indicate the need for higher density platforms. The term “density” is used to refer to the number of I/O channels (both analog and digital) per board or per FPGA. The need for increased density, along with the participation of many contributors involved in high-energy physics research, led to the creation of the PICMG MicroTCA.4 R1.0 standard. This standard defines a new set of specifications that provide shelf and AMC carrier support for rear transition modules (RTM) in order to add additional I/O expansion capabilities.
Nutaq’s Perseus 611x was developed to address the need for increased I/O density and high-speed interconnects. The Perseus 611x is a double-width AMC featuring a Virtex-6 FPGA, two HPC FMC sites, and RTM expansion. When carriers are designed with RTM capabilities, it is useful to route as many of the FPGA's GTX high-speed transceivers (and optionally Fat Pipes Regions 1 and 2) as possible to the RTMs. The flexible interconnect architecture makes it possible to establish dedicated high-speed and low-latency communication links between several boards. These links can also be used to route data to and from external subsystems using different transport protocols, including PCIe, SRIO, SAS, SATA, 10-GbE (XAUI), SFP, and XFP.
Figure 2: Perseus611x block schematic
Additionally, a double-width card like the Perseus611x doubles the number of FMC sites and doubles the front-panel I/O density when compared to traditional single-width AMCs like the Perseus601x. By interfacing twice as many channels to a single FPGA, large-scale acquisition systems like those used in linacs can benefit from lower per-channel costs, as well as higher system density. Manufacturers offer a wide range of FMC cards equipped with different channel configurations for their digital-to-analog converters (DACs) and analog-to-digital converters (ADCs).
Nutaq’s engineering team was recently put to the challenge of designing a high-speed ADC card with the lowest cost-per-channel in the industry. A few months later, the MI125-32, an HPC FMC with a 32-channel ADC (125MSPS, 14 bits) was born.
Figure 3: Nutaq's MI125-32 ADC FMC
With channel density in mind, engineers have leveraged Nutaq’s innovative "double-stack" concept. "Double-stack" takes advantage of the MicroTCA’s full-size form factor, enabling the use of two FMCs on a single AMC carrier. In a previous blog, we saw that the trick to implementing a double-stack FMC is to design a board that only requires the signals from a low-pin-count (LPC) connector to function. Instead of using an LPC connector to connect the board to a carrier, an HPC connector is used instead. Signals destined to both FMCs in the stack go through this connector to the extender FMC; signals for the extender FMC use the LPC signals, and signals for the top FMC use the extra signals available from the HPC. These extra signals from the HPC connector are then rerouted to an LPC connector on the extender FMC to be connected to the top board.
Figure 4 shows how signals are routed in double-stacked FMCs.
Figure 4: Double-stacked FMCs