Software-defined radio (SDR) is a current trend in the field of radio development. Previously, radio technologies were developed with static architectures. The radio resource allocation and the access network architecture were hardware-defined and thus not programmable or configurable.

Today’s trend is to make platforms as configurable as possible. Radio systems typically consist of an RF front-end and a baseband processing module. The RF front-end generally includes antennas for transmission and reception and hardware for frequency down-conversion. Multiple options are available for baseband processing; we can implement the processing algorithms with a general-purpose CPU or with a programmable chip like a digital-signal processor (DSP) or a field-programmable gate array (FPGA).

The providers of SDR development platforms use different approaches to make their platforms as “software-defined” as possible. Along with programmability, all the approaches aim at optimizing three other key features: flexibility, energy consumption, and computing power.  Developers select their hardware architecture as balance between these trade-offs. In this blog post, we describe and comment on two different current approaches: a “general-purpose CPU” approach and a “mixed approach”. Our analysis was inspired from an article posted by INSA-Lyon

[1].

The general-purpose CPU approach

In the general-purpose CPU approach to SDR, the platforms use common computer processors as a computing unit. Universal Software Radio Peripherals (USRPs) is a good example of this approach. High-frequency ADC/DACs sample the signal at an intermediate frequency (IF). An FPGA then converts the signal to baseband. The baseband signal processing (corresponding to the PHY layer) is then performed on the CPU, which is connected to the FPGA by a USB or Gigabit Ethernet link.

This approach provides the engineers with the benefits of an easy-to-program CPU. They may even accelerate their development through the use of model-based software tools like GNU Radio that implement many different processing algorithms. However, the actual general-purpose CPUs are not fast enough to implement the PHY layer required by the latest protocols, and the requirement for fast processing is growing faster than the processing power of the CPUs. Unless there is a move towards parallel processing, this kind of technology will only support older protocols for real-time implementation.

The mixed approach

The mixed approach is the one adopted by Nutaq. In this approach, the high-frequency ADC/DACs sample the signal, convert it directly to baseband, and transmit it to a high-resource Virtex-6 FPGA that can handle some or all of the processing. Generally, the PHY layer is built into the FPGA. The remaining processing, generally the MAC layer, can be implemented in a CPU that is linked to the FPGA by a Gigabit Ethernet or PCI Express (PCIe) link.

This is why it’s called the “mixed approach” – because both the FPGA and the CPU share the processing. This enables the user to benefit from the high-processing potential of the FPGA while providing user-friendly environments like GNU Radio for the remaining required processing. The latest protocols can be built on SDR platforms like Nutaq’s PicoSDR. With the PicoSDR, the FPGA is programmed with ISE (for directly coding the FPGA using HDL) or with user-friendly Simulink with Xilinx System Generator blocks and a Nutaq plug-in. Complex models like OFDM were achieved with this platform, thus saving a lot of time for people who design signal processing algorithms.

Using Nutaq’s Model-Based Design Kit (MBDK), engineers and researchers can reduce development time from months to weeks

For FPGA programmers, Xilinx’s System Generator enables the use of powerful model-based design tools. Programmers can build the system they wish to implement in the FPGAs as a model within Simulink and then generate the hardware description language (HDL) to program them.

Nutaq includes its MBDK with its FPGA-based platforms, instantiating the hardware within Simulink and allowing for the use of Xilinx System Generator to program the FPGAs. Moreover, the MBDK allows bit-true cycle-accurate simulation. This dramatically reduces the development time.

A set of Simulink blocks instantiate the Nutaq FPGA mezzanine cards (FMCs):

Another block ports the data to Simulink for hardware-in-the-loop simulation:

Finally, the Real-Time Data Exchange (RTDEx) blocks provide a framework to exchange data with a host device through the Gigabit Ethernet or PCIe links with the highest bandwidth and lowest latency possible.

The user can implement complex FPGA programs within a few days (and simpler programs within a few hours). The simulation is perfectly bit-true and cycle-accurate, so the user can rely on the results and expect them to happen once implemented in the hardware:

References:

[1] Software Defined Radio Architecture Survey for Cognitive Testbeds, Mickael Dardaillon, Kevin Marquet , Tanguy Risset, Antoine Scherrer, Universite de Lyon, Inria, INSA-Lyon, CITI, F-69621, Villeurbanne, France, URL:  http://arxiv.org/pdf/1309.6466.pdf