In this series:
- A Step by Step ADC/DAC Tutorial Series Part 1: Introduction
- A Step by Step ADC/DAC Tutorial Series Part 2: Overview of the ADAC250 FMC and the installation of the development software
- A Step by Step ADC/DAC Tutorial Series Part 3: Software installation validation and the first steps with MBDK
- A Step by Step ADC/DAC Tutorial Series Part 4: Project definition
In the previous post of this series, I showed a system design that used Nutaq’s Model-Based Design Kit (MBDK). In this post, I will explain how it was implemented in Simulink.
First of all, let’s make it clear that design and simulation are the first stages when working with the MBDK. During the first phase in this blog post, we will not be working with the hardware yet. Because the system is bit-true and cycle-accurate, we can expect the results to be the same during simulation as when the model is implemented in the FPGA.
The initial stage of the project was simply to test the analog-to-digital and digital-to-analog conversion blocks. To do so, we connected the ADC directly to the DAC, generated a simulation signal, and plotted the results in simulation using a Scope block from Simulink.
The System Generator and the FPGA board configuration blocks are used to simulate the Nutaq hardware using Xilinx System Generator. Nutaq’s blocks are in green in the diagram. There is a unique block from Nutaq’s blockset that represents the ADAC250 acquisition board.
By double-clicking the ADAC250 block, we can configure it as an ADC or a DAC. It is also possible to set it for channel A or channel B (the ADAC250 has 2 ADCs and 2 DACs). It is also in this window that one will set the binary point. The analog-to-digital conversion channels have a resolution of 14 bits and the digital-to-analog channels have a 16-bit resolution. Thus, 214 and 216 values in base 10 can be expressed on these two types of channels. The maximum number that an instance can express at the output of the ADC is 16384.
In this example, we wanted to limit the amplitude range of the signal from -1 to 1. So, we set the binary point so that only one digit is left before the point. This is why the binary point was set to 13 in the ADC and 15 in the DAC.
To plot the results for over a period of time, we need to set the time in the simulation parameters. This is quite basic for Simulink users. We select Simulation > Configuration, and then set the start and stop times. Next, we run the simulation and access the plot results by double-clicking the Scope Simulink block.
In our project we obtained the following results:
The results are what we expected: a sine wave is sent to the ADC then directly converted back to analog by the DAC. Therefore, we can conclude that the first stage of the model has worked and we can go on to the second phase.
The second stage is to implement the modulation part, as shown by the following diagram (taken from the previous blog in our series):
To achieve this, we will make use of one of the key benefits of model-based design and, I would even go as far to say with Matlab Simulink itself, a tool designed to accelerate development time: reusability. We will reuse the whole modulation part from a model that was previously made for single sideband modulation. The result is the following diagram:
The red blocks represent the modulation phase. In fact, some of these blocks are subsystems and were made in a previous model.
Once this was done, we obtained the same signal on the scope as we did in the previous step. The next step will be integrating the transfer of the data from the host computer into the system and out of the system back to the host. This will be achieved by using the real-time date exchange (RTDEx) IP core.
The functional block diagram will be as follows:
In this blog post we started to design the system we described in the previous posts. We achieved the digital conversion and converted the signal back from analog. We also could configure the modulation in the FPGA and make it work as well. In the next post of this series, we will configure the Ethernet to enable communication with the host PC.