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In my previous blog post, I showed the benefits of combining a processor with an FPGA when developing embedded digital signal processing (DSP) applications. While the FPGA's main role is data crunching, there are good reasons to add a processor, namely to perform other less demanding tasks. For example, processors (programmed in C or other programming languages) are more appropriate for sequential tasks like device initialization and dynamic configuration. As shown in the previous post, the Nutaq reference designs and tools embrace this trend and include a soft processor that can simplify and accelerate your development process.

While the benefits are clear, soft processors do not come for free. The first section of this post describes a typical soft-processor subsystem, using the MicroBlaze subsystem of the Perseus BSDK reference design as an example. The next section sketches a picture of the MicroBlaze subsystem's FPGA resource distribution, as its main drawback is likely the resources it consumes.

MicroBlaze subsystem

Soft processors, as processors, do not come alone. At the minimum, they require memory to store their program and intermediate results (stack, heap, etc). Peripherals are also essential for interacting with the system, such as audio/video/keypad functionality when interacting with a human. Other peripherals may also be necessary, like Ethernet, PCIe, serial ports, timers, and interrupt controllers, to name a few.

Most reference designs based on the MicroBlaze soft-processor share a similar structure. The peripherals change slightly depending on the devices surrounding the FPGA and the required functionality.

Figure 1 shows the MicroBlaze subsystem of the Perseus Board Support Development Kit (BSDK) reference design. There are different types of logic:

  • Logic inherent to the MicroBlaze, like on-chip memory, timer, and watchdog peripherals.
  • Controllers for external memory (DDR3 SDRAM and Flash). In this case, they are required to support the Linux operating system.
  • Logic to monitor and control the different on-board devices of the Perseus board like IIC and SPI controllers.
  • Logic to interact with the outside world, like RS-232 and Ethernet.

Figure 1: Microblaze system for the Perseus BSDK reference design

Figure 1: MicroBlaze system for the Perseus BSDK reference design

MicroBlaze subsystem resources

Table 1 lists the FPGA resources consumed by each element of the MicroBlaze subsystem for the Xilinx Virtex-6 family. The PCIe interface has not been included because it does not require the MicroBlaze to operate. Also, even if the RTDEx logic is controlled by the MicroBlaze, its logic is considered as user logic and is only present when required. The glue logic group includes all the remaining logic, like buses, system reset, debug logic, and clock generation.

 Table 1: Microblaze resources for the Perseus BSDK reference design

Table 1: MicroBlaze resources for the Perseus BSDK reference design

To understand these numbers better, Table 2 summarizes the percentage usage of the complete soft processor system for different Vitex-6 FPGAs. The devices followed by an asterisk (*) are devices supported on the Perseus board.

Table 2: Microblaze resources for the Perseus BSDK reference design

Table 2: MicroBlaze resources for the Perseus BSDK reference design

Even if the MicroBlaze system does not require a lot of fabric logic, it is not negligible in terms of BRAM and slices, especially for the smaller FPGAs. The good news is that almost all the FGPA's DSP processing capacity (DSP48) is left to the user applications. This means that almost all the logic that implements multiplications, additions, and multiply-accumulate operations are left to the user. These basic operations are the building blocks of many DSP functions, including filtering, correlation, and FFTs.

Is the MicroBlaze core worth it?

Usually, soft-processors are beneficial since they simplify and accelerate the embedded system development. Nevertheless, in some cases, designers might not be able to afford the extra logic required by a soft-processor subsystem. For example, a designer might at the end of the design process want to reduce the FPGA size (e.g. for cost reduction, limited final product size, or power budget). In this case, different solutions are available. In my next post, I will present some potential optimizations that considerably reduce the amount of required logic without impacting too much on the application.