Our team is now working on the packaging and testing of release 6.5 for our ADP software tools, which will be available at the end of Q2. In the meantime, I’d like to bring to your attention to some of the new features that will be introduced.

Here's a list of new features that will be part of the ADP Software Tools 6.5 – MicroTCA Edition:

  • Command line interface (CLI) based firmware update tools
  • Multiple FPGA bitstream selection at boot-up
  • New LVDS core enabling the use of the Mestor interface
  • ADAC250 streaming support
  • ADP software goes open source
  • WRxG product support

In this post, I’ll discuss the first three new features (the rest will be covered in the next post).

CLI-based firmware update

Starting with release 6.5, new tools will be available to make it easier to update the Perseus firmware. Previously, to perform a firmware update, a serial connection to the Perseus was required and approximately 30 steps were necessary to update everything in the flash memory.

Starting with release 6.5, the process for updating the Perseus firmware will be simplified. As long as the Central Communication Engine (CCE) of the Perseus is at least at version 2.11.13, all future updates of the flash memory blocks (uboot, kernel, dtb, jffs2, CCE) to support new releases will be performable from the CLI interface. For most users, only the update of the CCE to a version supporting these new commands will require the old update procedure. Once the CCE is updated, everything can be performed using the CLI.

Multiple FPGA bitstream selection at boot-up

Release 6.5 has a very useful new feature – we have reworked the memory map of the Perseus flash memory to make room for two separate bitstreams and implement what we call “multiple FPGA image boot-up”.

This feature is available as soon as the Perseus is running release 6.5 firmware. It enables you to store two different bitstreams in the flash memory, provides the functions to program them separately, and lets you select which one will be programmed in the FPGA at the next boot-up. This feature will be great for people who need to share a system but are working on different applications (e.g. in a lab, for example).

New LVDS core enables the use of the Mestor interface

Included in release 6.5 is a new generic LVDS module that enables the use of the Perseus FPGA I/Os in either asynchronous (GPIO) or synchronous (bus-like) mode. Many LVDS cores can be instantiated in the same design so hybrid (GPIO + bus) configurations and even configurations with more than one synchronous bus are possible.

This generic LVDS core was designed with the Mestor interface in mind. The Mestor interface is part of the PicoDigitizer family and is used by the FPGA to communicate with the external world.

Figure 1  PicoDigitizer250 Mestor interface

Using the Mestor interface, PicoDigitizer users can, for example, control the front-end of a system connected to their device.

Release 6.5 includes an example that shows how to use the LVDS core to control the Mestor interface of the PicoDigitizer. Figure 2 shows its architecture.

Figure 2  Mestor interface example

As you can see, release 6.5 of the ADP software tools will include many useful new features. I’ll cover the rest of the features in my next blog post.