In this series:
- The Record and Playback Module: Part 1- Use Cases and Development Flow
- The Record and Playback Module: Part 2- Implementation and Record Mode
My previous two blog posts discussed the common use cases of the Record and Playback FPGA module as well as record mode implementations. In this post, we conclude the series by discussing the playback mode’s features and common uses.
When using the module in playback mode, the user can:
- Play back data from DDR3 memory to the user logic.
- Play back data to different destinations (on different ports).
- Play back a finite number of samples. The transfer size in bytes must be specified.
- Play back data once or continuously.
- Trigger the playback from an external signal or from software.
The maximum tested bandwidth of playback mode is 5.7 GBytes per second.
The following diagram illustrates the data flow within the playback module:
Playback module reads from memory have a width of 256 bits. The number and width of the playback ports are user-configurable. The following table shows the valid combinations for these two variables:
Note: All the ports must use the same width. The unpacker FIFO initiates reads of 256 bits in the memory to feed each port contiguously; the product of the number and width of these ports cannot exceed 256.
Just like in record mode, the data for each channel must be stored contiguously in memory. Using an example similar to the one in my previous blog post, a waveform is loaded in memory. The user has configured two playback channels with 16-bit widths to send an IQ waveform to the DAC on the FPGA mezzanine card (FMC). Channel A holds the I information and will be played back on port 0, while channel B holds the Q information and is played back on port 1.
The data requires the following arrangement when it is stored in memory prior to playback (ChA – 0 means channel A, sample 0):
The host PC uses the Record and Playback module’s host to memory mode to transfer the data to the DDR3 memory.
Triggers and start address
Just like with record mode, playback can be triggered by an event external to the FPGA core or directly from software. After configuring the playback mode, the user must specify a start address, which is the address in memory of the first byte to be played back. The following use cases demonstrate playback options.
Use case 1: The user has a waveform (in a binary file) on the host PC. The user wants to play it back through his or her processing logic and output it on the FMC’s DAC when a trigger signal is received on the front panel.
First, a host to memory transfer will be used to load the binary file into the Record and Playback DDR3 memory, at address 0. The user will then specify a playback transfer of the size corresponding to the file size, using a start address of 0 and an external trigger. Upon the trigger event, the playback module will start reading data from memory at the specified address and enable the processing logic to read this data on the playback port until the file size is reached.
Use case 2: The user wants to record a waveform acquired by from an external source by the FMC’s ADC and then play it back on the FMC’s DAC.
Part 2 of this blog series described how a host PC retrieves a trigger address when the data recording is finished. The trigger address corresponds to the location of the recording’s first byte in memory. Specifying this address as the start address makes it possible to play back the recorded sequence directly, without having to import the recording on the host PC. The software trigger enables the user to start the playback at will, without the need of an external event.
Single and continuous transfer modes
When configuring the playback module, the user must specify the transfer mode: single or continuous.
In single mode, the playback transfer will stop after the specified size is reached. In continuous mode, upon reaching the transfer size, the playback module will restart reading from the start address and do so continuously until stopped by the user.
The continuous mode lets the user play back periodic signals (for example, with a sine wave, only one cycle has to be stored in memory) or play back the same sequence over and over again, without needing to reconfigure the transfer.
In this blog series, we’ve covered the most common use cases of the Record and Playback module. We’ve also explained its features and implementation details. It’s my hope that this series has successfully demonstrated how invaluable this tool is when developing signal processing algorithms on FPGA platforms and that these features help to accelerate the prototyping cycle.