In this series:

In the first post of this series, we created a pcore from a System Generator model. The Gateway In and Gateway Out blocks are necessary to create ports for interacting with the other pcores in our FPGA. Here’s the model we used in Part 1:

From this point on, our pcore can be considered a blackbox with the following interfaces:

  • Input port – Gateway In, a 1-bit input vector
  • Output port – Gateway Out, an 8-bit output vector

Let’s open our XPS EDK reference design. For ZeptoSDR user, the FPGA reference design is located at C:NutaqZeptoexamples_zedboardzedboard_radio420s_bsdk. In this folder, you will find a folder named bitstream. Make a copy of this folder and then rename it to bitstream_release. Next, rename the original bitstream folder to bitstream_cnt_sysgen.

In the bitstream_cnt_sysgen folder, open the zedboard-adp.ppr PlanAhead project file. You should see the following window:

This PlanAhead project includes everything required to generate the default examples for the ZeptoSDR board. Under Design Sources, expand arm_system_stub – STRUCTURE and double-click on  arm_system_i. This starts Xilinx Platform Studio (XPS), where we will add our pcore.

After the following window appears, click on the Add/Remove IP Repositories icon (top left):

Click the Add path icon and select the folder where your pcore folder was generated (for example, if my pcore folder is C:/work/ADP_6_3/EDK_pcore_Cnt_Sysgen, the folder to select would be C:/work/ADP_6_3/):

Click OK to close the above windows. You should have now a new branch in your pcore library called USER. Maximize this branch and you should see a pcore called cnt_sysgen_axiw:

Right-click on this pcore and select Add IP. A prompt box will appear, asking you if you want to add one instance of this pcore in your design. Select Yes.

The following window will appear:

Click OK. A second window will appear:

Select User will make necessary connections and settings and click OK. Now, select the Bus Interfaces tab. This tab lists all the pcores included in the basic ZeptoSDR reference design plus our new pcore that we just added.

Select the Ports tab. Find the cnt_sysgen_axiw_0 pcore and then maximize the instance to show its ports:

These ports are linked to the Gateway In and Gateway Out blocks in the Simulink model. Basically, the pcore that we created in Simulink is a blackbox with input and output. However, in the Range column, you will see the bit width of these connections (

[0:7]). The size of the vector is good, but the direction is NOT if you are using Xilinx software version 14.5 or older! This is a known bug by Xilinx and should be fixed in 14.6. So, if you do see the same screen as shown on this post, we need to change the vector direction manually. If not, you are free to skip the bit-flipping section of the next blog post and go directly to the port connection section.