In this series:

System Generator is a key software tool for accelerating the development of complex digital signal processing (DSP) applications on Xilinx field-programmable gate arrays (FPGAs). The ‘cycle true’ and ‘bit true’ simulation of the DSP blocks saves the developer lots of time. I personally use System Generator for all my DSP applications. Nutaq’s orthogonal frequency-division multiplexing (OFDM) reference design is a great example of a complex application developed with this tool. Without any hardware description language (HDL) coding skills, one can achieve similarly complex applications on real hardware. On PicoSDR systems, it’s even easier as Nutaq’s Model-Based Design Kit (MBDK) software eliminates the hardware interfacing part of the implementation. The developer can directly generate his or her final bitstream directly from the System Generator model.

Unfortunately, on other Xilinx-based platforms (like the ZeptoSDR), the MBDK software isn’t available. Is it still possible to save time by using System Generator with these platforms? The answer: yes!

As an example, let’s develop a very simple application on Nutaq’s ZeptoSDR. This board is built around the Xilinx Zynq processor and Nutaq offers its free Board Software Development Kit (BSDK) with it. The BSDK includes a reference design packaged as an Xilinx Platform Studio (XPS) EDK project file. So how do you develop a DSP application under System Generator and then move it to an XPS EDK project?

System Generator has always been able to generate a netlist and/or a bitstream for supported Xilinx FPGAs. However, starting with version 13.4, System Generator can directly create an EDK pcore from a System Generator model. It also adds the necessary AXI wrapper if you plan to connect your pcore to the AXI bus.

First, you need to have the two following blocks in your model: the System Generator token and the EDK Processor block.

The EDK Processor needs to be configured as ‘EDK Pcore generation’. You then select ‘Export as a pcore to EDK’ in the System Generator token:

The next step is to select your FPGA (a Zynq xc7z020-1clg484 for the ZeptoSDR) and the target directory where you want your pcore to be generated.

Afterwards, it’s up to you to develop your own System Generator model. This model should include two types of blocks: DSP blocks (blue blocks with the Xilinx logo) and Gateway In/Out blocks (yellow blocks with the Xilinx logo). The Simulink blocks (white) are used for simulation only. Here’s a very simple model:

At pcore generation time, the blue blocks will create the necessary logic to implement an 8-bit counter and the yellow blocks will create a boolean input port and an 8-bit output vector with the names shown on the model (Gateway In and Gateway Out, respectively).

When the simulation is done, the next step is to create your pcore by clicking ‘Generate’ using the System Generator token.

After a few seconds, everything is ready to be implemented in the XPS EDK project, which will be covered in Part 2 of this blog series.