Xilinx System Generator is a key software tool for accelerating the development of DSP applications on Xilinx FPGAs. In the Rapid DSP Application Development blog series, we see how to harness its power step-by-step using Nutaq’s ZeptoSDR (Zynq processor). We generated a very simple application (a counter) for an example, but the guidelines are still valid for more complex applications.

Here’s links to the four posts in this series:

Each part in this series is a continuation of the previous post, so be sure to read them in order.

A recap of Part 1

In Part 1, we start the series by developing a very simple application on Nutaq’s ZeptoSDR platform. After setting up the project, we add our own custom DSP blocks. and generate our pcore file from our model.

A recap of Part 2

In Part 2, we consider the generated pcore as a blackbox with a set of interfaces. We then import an instance of this pcore into our design.

A recap of Part 3

Part 3 describes a necessary bug fix for those running System Generator 14.5 or older as well as the necessary port configurations. The post ends with netlist generation.

A recap of Part 4

In Part 4 we add ChipScope to the model so we could validate its implementation. To add ChipScope, we used the Find command to locate and add the necessary port’s net name and then generated the bitstream. Finally, we ran ChipScope Analyzer and validated our application.