Nutaq has decided to provide a new reference design with the Radio420X FPGA mezzanine card (FMC) for users who want to develop on the Xilinx Virtex-7 FPGA. The Virtex-7 chip, found on Xilinx evaluation boards like the VC707 or VC709, has high-performance input/output (I/O) banks. This means that the highest voltage of the bank can be 1.8V1. For this reason, the board’s VADJ for the FMC connectors is fixed at 1.8V, which can limit the number of compatible FMCs.

To address this issue, Nutaq now offers a 1.8V version of its popular radio FMC, the Radio420X2. Xilinx Virtex-7 boards can now be used as carrier boards in software-defined radio (SDR) solutions that integrate the Radio420X as the RF front-end.

Reference design

A reference design project using the Xilinx VC707 evaluation board will be freely available with any purchase of the new Radio420X 1.8V3. The reference design is similar to ones previously available for the Xilinx ML605 board. The project was developed with the Vivado Design Suite, v2013.3. Inside the Vivado project, a Xilinx Platform Studio (XPS) subsystem is used to instance a MicroBlaze soft core microprocessor as well as the other AXI cores.

On the VC707, a Radio420M (2×2 MIMO) can be connected on the FMC1 connector as it’s a full high-pin count FMC site. On the FMC2 connector, the HB bank is not routed to the FPGA so only a Radio420S (1×1 SISO) can be used4.
On the VC709, the two FMC connectors are fully routed to the FPGA and two Radio420M cards can be used to make a 4×4 SDR solution.

The reference design package provides an AXI Lite core for the Radio420X FMC. The provided application programming interface (API) enables the radio FMC to be configured by the MicroBlaze in the C programming language.
Once the Radio420X is configured, data can be received to and from the RF front-end. The ports on the Radio420X FPGA core provide direct access to the raw I and Q 12-bit samples. In the reference design, a direct digital synthesizer (DDS) sends the I and Q samples to the Radio420X core. By connecting a spectrum analyzer to the transmit (TX) MMCX connector, the output RF signal can be monitored.

With the default Radio420 core and API, automatic calibration functions are available for improving the single-side band and the local oscillator leakage rejections of the RF front-end.

By connecting a signal generator to the receive (RX) MMCX connector, the I and Q samples can be monitored with the Debug tool provided by Vivado. The Debug tool is the new version of Chipscope and is accessible directly from the Vivado window.

Conclusion

The new reference design is a good starting point for anyone who wants to start developing SDR applications on Virtex-7 devices. The benefits of the large Virtex-7 FPGAs when developing complex and computationally intensive SDR applications can now be combined with Nutaq’s high-end RF FMC. The reference design also shows how the Radio420X can be used inside a Vivado project and how easily the RF front-end can be reconfigured and calibrated using the provided API.

References

1 http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
2 http://www.nutaq.com/blog/designing-fmc-radio-compatible-virtex-7-evms
3 http://www.nutaq.com/support/fmc-bsp-reference-designs
4 http://www.nutaq.com/blog/nutaq-fmc-compatibility-chart