In a previous blog post, my colleague described how to use Global Positioning System (GPS) clock disciplining in an RF system and briefly mentioned the PPSSYNC core available in Nutaq's ADP Software Tools Release 6.4

[1]. In this blog post, I show how GPS clock discipline implemented on the Radio420X or ADAC250 FPGA mezzanine card (FMC), found on Nutaq’s Perseus 601, a Virtex-6 FPGA FMC carrier board [2,3,4].

GPS clock discipline implementation

Figure 1: Partitioning GPS clock discipline implementation

Figure 1: Partitioning GPS clock discipline implementation

The implementation of GPS clock discipline is partitioned into two parts: FPGA logic and the software driver, as shown in Figure 1. In Figure 1, the FMC’s on-board voltage-controlled crystal oscillator (VCXO) is driven by a small-footprint Serial Peripheral Interface (SPI) controller in the FPGA. The PPSSYNC core removes unexpected electrical glitches from the GPS pulse per second (PPS) line before performing cumulative frequency error measurements. The PPSSYNC core is accessible via custom registers on the Perseus 601X’s MicroBlaze processor.

Figure 2: A closed-loop GPS clock discipline topology

The PPSSYNC driver is an implementation of a well-known proportional integral (PI) algorithm that is widely used in telecommunications and industry process control for tuning the on-board VCXO frequencies (shown in Figure 2). It is implemented in user space so that user can access the driver either from a remote host via the Extended Application Programming Interface (EAPI) or from user application inside the MicroBlaze processor.

The cold-start values used by the reference DAC and PI controller input parameters are user-programmable. The PPSSYNC driver is expected to tune the on-board VCXO via the SPI controller in the reverse direction of the measured error to keep the actual frequency error as low as possible. When the desired clock signal enters into the locked or hold-over mode of the GPS PPS signal, the current reference DAC and the PI controller parameters will be updated and stored in the file system, in order to have a fast lock time in the next run.

Building an user application using PPSSYNC

Figure 3 shows the typical flow of a PPSYNC application.

Figure 3: PPSSYNC application creation flow

The first step taken by a programmer when building a PPSSYNC application should always be to detect the presence PPSSYNC core. If the PPSSYNC core has already been run, the user application must stop the core to ensure known states for all the components of the PPSSYNC at startup.

If the PI controller parameters and the reference DAC value are previously stored in the file system, it is necessary to use them when initializing the DAC and PI controller to achieve a faster lock time. Otherwise, manually provide the initial values for the DAC and PI controller before starting the clock discipline using PPSSYNC driver.

Conclusion

PPSSYNC is an implementation of clock discipline in Nutaq’s Perseus 601 carrier board that uses the PPS input from GPS and VCXO available in Nutaq's Radio420X and ADAC250 FMC modules. It’s available in Nutaq's ADP Software Tools Release 6.4.

References

[1] Jean-Dominique Gagnon. (2014) GPS disciplining of an RF system clock. [Online]. http://www.nutaq.com/blog/gps-disciplining-rf-system-clock
[2] Nutaq Inc. (2014) Radio420X. [Online]. http://www.nutaq.com/products/radio420x
[3] Nutaq Inc. (2014) ADAC250. [Online]. http://www.nutaq.com/products/adac250
[4] Nutaq Inc. (2014) Perseus 601X. [Online]. http://www.nutaq.com/products/perseus-601x