In my last blog post I gave a sneak preview of the MO1000 FPGA mezzanine card (FMC) that we are currently working on. In this post, I go a bit deeper and describe how we designed the clocking subsystem to achieve the best possible synchronization between all the channels of a single MO1000-8 FMC (8 DAC channels) as well as with an MO1000 FMC stack, also called MO1000-16 (16 DAC channels).

First, here's a diagram of the MO1000 FMC's clocking subsystem. I'll go over the important parts and the design choices we made to ensure maximum synchronization between all the channels.

Step 1 – Clock source selection

Users will be able to choose the clock signal used by their single or double-stack MO1000 system from four sources:

  • The 125 MHz oscillator of the MO1000 FMC, a CCHD-575 from Crystek. This is the lowest jitter clock oscillator in such a small package. It has a typical phase jitter of 82 fsec RMS at 100 MHz. It also has an ultra-low phase noise floor at -168 dBc/Hz.
  • A single-ended external clock signal fed to the MO1000 FMC through the front connector
  • A standard differential clock signal originating from the FMC carrier, CLK2_BIDIR, sent through the high-pin-count (HPC) pins K4(+) and K5(-)
  • A standard differential clock signal originating from the FMC carrier, CLK3_BIDIR, sent through the HPC pins J2(+) and J3(-)

The selected clock signal source is then fed to the Texas Instruments CDCE62005 clock generator.

Step 2 – System clock generation

Using the clock signal input at the CDCE's reference pin 1 (REF1), the high-speed clock signals that will be used by the different parts of the system are simultaneously generated on the OUT2 and OUT3 clock outputs. These two clocks have the exact same frequency and are phase-aligned. This makes it possible to synchronize the digital-to-analog convertors (DACs) of two MO1000 FMCs when used in a double-stack configuration.

Step 3 – System synchronization

To synchronize an MO1000 double-stack system, special care must be taken so all four DACs receive a clock signal that is phase-aligned. To do this, we use the two clocks generated on OUT2 and OUT3, which have the same frequency and are phase-aligned, and we make sure that these signals travel the exact same distance before being used as a clock source for their respective card.

As shown in the diagram (blue signals): when a slave MO1000 (the one further from the carrier in a stack) is connected on top of a master MO1000, its B signal is connected to the master’s A signal through the FMC connector. The total distance traveled by the signal generated on the OUT3 pin of the master’s CDCE clock generator until it reaches the slave’s REF2 clock input multiplexer is equal to the following equation:

length of A + length of B + distance traveled in the FMC connector + thickness of the PCB

We then had to make sure that the length of the C path was equal to the result of this equation to ensure our design would maximize the phase-alignment of the four DACs (16 channels) inside an MO1000-16 system. Note that since the PCB design is identical for master and slave FMCs, the path between the REF2 signal multiplexer and the REF2 pin of the CDCE62005 is identical, so this doesn’t need to be taken into account when calculating the distance traveled by the signals.

The same kind of care was taken when routing the DAC’s clock signals (shown as pink and orange in the diagram). Again, we made sure that all four of these signals had the exact same length to optimize synchronization between all the channels. These two clock signal pairs are generated from the REF2 clock input pin of the CDCE62005, which takes as an input either the OUT2 signal of its own CDCE clock generator if acting as the stack master or the OUT3 signal of the master FMC if acting as the stack slave.

Hopefully after reading this overview of the MO1000 FMC's clocking, you better understand how we designed it (and the MI125 FMC, for that matter) to maximize signal synchronization when used in a double-stack configuration and to offer you a good product to work with in applications where phase alignment between generated signals is critical to achieve success.