In this series:

The Kermode platform – Part 2

In the blog post, Using FPGA technology for radio astronomy, my colleague Jean-Benoit Larouche introduced the Kermode board, which was developed by Nutaq in collaboration with the Dominion Radio Astronomy Observatory. In this post, the first in a series about the Kermode platform, I describe the board’s hardware features and walk-through a typical Kermode system. Subsequent posts in this series will describe the data paths and interconnections between the processing units as well as the hardware’s support software.

The Kermode Hardware

Kermode platform

The Kermode platform is designed to accept a massive amount of data from either the front or back panels, provide the means to process the data, and then output it after processing. All the platform’s hardware features are geared towards achieving these goals. The main features of the Kermode board include:

  •  ATCA form factor
  •  8 Virtex-6 SX475T FPGAs
  •  4 high-pin count FMC sites
  •  Zone 1, 2 and 3 back panel connections
  •  Gigabit Ethernet connections on both front and back panels

The Kermode’s 8 Virtex-6 FPGAs are divided in three functional groups:

  • There are four ”front” FPGAs, F1 to F4. These FPGAs are connected to the FMC sites and handle the data reception on these ports.
  • There are three slave ”rear” FPGAs, R1 to R3.
  • There is one master ”rear” FPGA, R4, which performs board management and control.

Each FPGA interfaces with two DDR-3 SDRAM SODIMM modules. Each module supports up to 4 GBytes, resulting in an aggregate memory capacity of 64 GBytes. This memory may be used to store the intermediate results of memory-intensive algorithms or to record full-rate digitized signals for post-processing or analysis.

Typical Kermode system

The Kermode platform is designed for use in an ATCA chassis with other units of its kind. The back panel mesh of an ATCA chassis permits multiple data path configurations, enabling users to heavily customize the system.

Data is typically inputted into the system through the Kermode FMC sites, the ATCA mesh, or a custom rear-transition module. The data is processed within the front and rear Virtex-6 SX475T FPGAs. It can then be exchanged through the ATCA mesh to other platforms in the system for further processing. When the processing is complete, the data is outputted through the FMC sites to an external destination.

Master FPGA (R4)

The master FPGA handles the board Gigabit Ethernet connection, received from either the front panel RJ-45 connector or the ATCA backplane.

A MicroBlaze processor is instantiated within the FPGA logic. The processor runs an onboard distribution of Linux that provide a TCP/IP stack, enabling the Kermode to communicate with an external PC through the Gigabit Ethernet port.

The MicroBlaze processor also has access to:

  • 128 MB DDR3 memory, dedicated to run the Linux distribution.
  • 2 flash memory devices, whose purpose is to store the Linux distribution as well as the FPGA configuration files. A future blog post will address the Kermode booting and configuration process.
  • The main PLL, which distributes clocks to the whole board.
  • FPGA configuration links to the other FPGA. The MicroBlaze processor is able to configure all the FPGAs at system boot or any other time, with a configuration file stored in flash or from an external host PC.
  • Inter-FPGA control communication through the Starlink interface.

The master FPGA logic handles all the other connections to the slave FPGAs. These connections will be described in the next post in this series. The user can also instantiate his or her own processing algorithms within the master FPGA.

Front FPGAs (F1-F4)

Each front FPGA is connected to its high-pin count FMC site. The 16 multi-Gigabit transceivers as well as all the LVDS signals are routed to the FMC connector. The FMC sites are used to transfer data between the platform and an external source. The typical FMC cards are ADC/DAC cards with sensors and actuators or high-speed connection cards, supporting protocols like 10-Gigabit Ethernet. Most of the Virtex-6 SX475T’s logic is available to the user for processing algorithms.

The front FPGA interconnections within the platform and the system will be described in the next blog post of this series.

Rear FPGAs (R1-R3)

The rear FPGAs hold processing logic and provide an interface to the ATCA backplane. The rear FPGA interconnections within the platform and the system will be described in the next post in this series.

Additional information

For more information on the Kermode platform, see to the product brochure.