In this series:
- How Nutaq’s Products Speed Up Your Design Flow When Using Xilinx System Generator: Part 2
High-level tools for designing FPGA-based high-performance DSP systems
It’s not a secret that the design complexity of high-tech embedded applications is still rapidly increasing in response to consumer demand. For applications that require intensive processing, ASICs offer high performance and a low high-volume price, while FPGAs tend to beat them on non-recurring engineering (NRE) costs and also offer a shorter time-to-market. The technology advances of the last decade make FPGAs even more attractive as their performance has significantly improved. Furthermore, FPGAs are no longer just programmable logic – they can integrate silicone cores for common functionality like Ethernet, PCIe, memory controllers, and microprocessors, thus making them a smart choice for System on a Chip (SoC) designs.
Design tools are trying to keep pace with the growth in complexity. While schematics and HDL editors were once widely used for FPGA development, designs nowadays integrate different IP cores (bought or developed in-house) and use plenty of different tools. Some parts of the design might still be done with HDL languages, but others are now developed with higher-level tools like HDL Coder and SystemVue. There are also software development environments that convert C code directly into programmable logic gates.
For signal processing applications like data acquisition systems (DAQ), Xilinx System Generator is a good, widely used choice. It extends Simulink to provide designers with a modeling environment that benefits from all of the MATLAB advantages. This kind of tool allows you to simplify and fasten the development of signal processing applications that previously would have been a major challenge with HDL. This is the first of a two-part blog that showcases typical development methodology when using System Generator to design logic. The second blog will show how Nutaq’s products can save you time and effort when using System Generator. System Generator as a part of a larger design System Generator is often used to implement a portion of a larger design. It is well suited for implementing signal processing functions like filtering, data encoding/decoding, and mixing, but is less appropriate for designing external interfaces or sophisticated control paths. I personally have developed tens of designs that integrate System Generator sub-modules, from direction-finding applications to digital pulse processing algorithms for baggage and cargo scanning. In each design, the following 5-step methodology was used.
1. Algorithm development
The first step is to identify which parts of the design might benefit from System Generator and the MATLAB environment. System Generator includes all the basic blocks like adders, comparators, and registers. It also includes sophisticated functionalities like filters and FFTs. Moreover, it benefits from MATLAB’s rich test bench environment, as MATLAB lets you easily generate sophisticated stimulus and analyse the results.
For example, let’s assume the simple case of a filter design (Figure 1). An ADC output goes to the FPGA where filtering is applied. The filtered samples are then transmitted to a PC.
Figure 1: System Generator filter design example
In this particular case, you might want to evaluate how many filter coefficients are necessary to implement the required characteristics. You might also try different coefficient resolutions to see the impact on the filter overshoot response or its rejection of specific frequencies. Algorithm development is often an exploratory process, one where diverse approaches and settings are tested and compared in terms of performance and resource usage.
2. Netlist/HDL generation
Once you have completed your design and are satisfied with the test results, you need to generate a netlist or HDL files to include into your larger system. To build your System Generator sub-module, add the System Generator token inside your model (the red block shown in Figure 1). By double-clicking it, you can choose your compilation mode, synthesis tool, and select the target FPGA device.
All System Generator logic is delineated from the rest of the Simulink logic through the use of Gateway In and Gateway Out blocks (the yellow blocks shown in Figure 1). The Gateway In blocks convert MATLAB double precision representation to fixed-point representation and continuous time signals to sampled data. The fixed-point precision and the sampling period are specified within the Gateway In block. The Gateway Out blocks convert fixed-point representation back to double precision.
Figure 2 shows the example VHDL entity generated by the tool. The names of the inputs and outputs that appear in the entity declaration are the ones used to label the Gateway In and Gateway Out blocks. Two additional signals are present (clk and ce) for the model clock and clock enable signals.
Figure 2: VHDL entity
3. Combine the generated part into a whole working design
You now have a netlist or HDL files that realize the wanted functionality. The next step is to integrate this sub-module into the whole design.
First, let’s introduce the term BSP, which stands for board support package. Many suppliers provide BSPs with their hardware. A BSP usually includes software drivers to initialize and configure specific devices as well as basic FPGA blocks for peripheral interfaces. These are sometimes called reference designs, from which you can start your own FPGA development. If the board is built in-house, you might even be the one responsible to develop it! We can then summarize that the work to do at that step consists of including the generated sub-module into the BSP.
In our simple example, it would probably take a couple of hours to connect the ADC to our sub-module filter. You would look at the reference design source files, see where the ADC input and its clock are, and then make the proper connections.
It might be trickier to connect the filter outputs since we wanted to send the filtered samples to the PC. Some extra logic might be required (depending on BSP and the link between the FPGA and the PC). For example, an Ethernet link might be available and part of the reference design, but if the BSP does not provide any logic to format Ethernet packets with samples, some more complex logic development might be required.
For more realistic designs with tens of ports, this step usually takes a significant amount of time. Even if the BSP offers most of the required functionalities, the connections often necessitate a deep understanding of the BSP implementation details.
The last two steps (4 and 5) are part of the normal development process and are not unique to using System Generator as a sub-module development tool.
4. Generate a bit file or simulation file of the complete design
At this step, it’s the synthesis tool that does the job for you. It generates a bit file or simulation file of your complete design.
5. Simulation or hardware tests
Even if the sub-modules have been tested individually, integration of the overall design may still require extensive testing. Some people prefer testing directly on hardware when available.
How can Nutaq’s products accelerate this process?
As I previously explained, these are key steps to complete when using System Generator to model functionality. System Generator can significantly help you to ease and accelerate your development of complex DSP algorithms. The amount of effort is mostly determined by the required functionality to implement. Considerable effort is required to combine your System Generator sub-modules with the BSP. That’s where Nutaq’s products greatly help you. The secrets will be revealed in my next post.