A new version of Nutaq’s Advanced Development Platform (ADP) Software Suite will be released later this month: ADP 6.4. To support this new software, a new GNU Radio plug-in, with a new architecture, will also be released.
Previous plug-in: gr-radio420
The previous GNU Radio plug-in, gr-radio420, was developed to use the default FPGA design of the Radio420 in the GNU Radio environment. It was possible to configure the radio parameters at initialization and to stream raw I/Q data with the Radio420 RF front-ends.
This plug-in works well but is only able to handle a limited range of applications. It assumes that a streaming channel (RTDEx channel) for each RF front-end is needed. This statement is true when raw data is streamed directly to the RF front-end. However, when signal processing algorithms are run inside the FPGA, the data transfer from an external computer to the FPGA platform is not necessarily raw I/Q data. For example, the data could be a voice or video stream. The FPGA logic can modulate the data to generate the raw data stream for SISO applications and even generate many raw data streams for MIMO applications.
New Plug-in: gr-nutaq
To improve flexibility with custom FPGA designs and to access the full potential of Nutaq’s API, a new modular GNU Radio plug-in has been developed, gr-nutaq. Instead of having one Radio420 configuration block and one Radio420 streaming block, these blocks have been split into multiple blocks. The new blocks are intended to match the architecture of the FPGA design in order to simplify the interaction between the host application and the FPGA logic flow.
First, a carrier board must be instantiated in the GNU Radio environment. The carrier block specifies the platform’s IP address and carrier type. Currently two carrier types are supported:
- Perseus: For PicoSDR platforms or Perseus-based µTCA systems
- Zedboard: For ZeptoSDR platforms or Zedboard-based systems
Once the carrier board is defined, every other Nutaq GNU Radio plug-in block must link to its carrier ID. This enables several carrier boards to be used in the same GNU Radio project with different configurations.
There are two types of Radio420 blocks: one to configure the reception path and one to configure the the transmission path. These blocks are used to configure the different parameters of the Radio420, like RF frequencies, data rate, analog gains, and filters. When a Radio420 in double-stack configuration (MIMO) is used, two RX and two TX Radio420 blocks must be instantiated.
RTDEx sink and source blocks are available for easy and direct data transfer between the host application and the FPGA design. Each RTDEx channel implementation with its counterpart in the FPGA can be seen as a data pipe with a flow control mechanism.
Different RTDEx media types can be selected (depending on the carrier board). Ethernet can be used when using a Perseus (PicoSDR) or Zedboard (ZeptoSDR) carrier. The PCIe interface can only be used with the Perseus hardware.
For embedded GNU Radio applications on the ARM processor inside the Zynq SoC (Zedboard), AXI RTDEx can be selected to transfer data between the processing system and the programmable logic.
When several RTDEx channels have the same throughput and need to be synchronized, several RTDEx channels can be instantiated inside the same RTDEx sink or source block.
In this synchronized mode, the data is sent and received on all RTDEx channels using a round-robin scheduling algorithm. Since each block is independent in the GNU Radio environment, this mode lets you evenly share the bandwidth between all the channels, thus avoiding the starvation of an RTDEx channel.
Custom register blocks
Custom register blocks can be used to read and write data within the FPGA design. The write operation can be triggered by a variable or by a data stream. These blocks enable the host application to dynamically control the FPGA.
The following example shows a Digital Up Converter (DUC) implemented in the FPGA design. It upsamples and shifts the frequency of the signal provided by the GNU Radio application. The result is then sent to the Radio420 RF front-end. Only the Radio420 TX path is used in this example.
The GNU Radio host application configures the Radio420 TX front-end, initializing the custom registers and continuously streaming signal source data to the FPGA design.
The “Complex To Float”, “Float To Short” and “Interleave” blocks are used to create a 16-bit (I and Q) sample stream from the initial complex stream.
The FPGA design was also developed with the Nutaq Model-Based Design Kit (MBDK) and the project is illustrated in the following figure.
Almost all the Nutaq blocks in a model-based environment have their counterpart in the GNU Radio environment. The Radio420S DAC channel 1 in MBDK is configured by the Radio420 TX block in GNU Radio. The custom registers 0 and 1 configure the respective up-sampling rate and the frequency shift in the MBDK and are controlled by the Custom Register blocks in GNU Radio.
Finally, the RTDEx I/Q 16-bit stream, at the input of the RTDEx block in GNU Radio, is transferred to the FPGA. The FPGA RTDEx interface is a 32-bit wide First In First Out (FIFO) memory. When there is data ready to be read in the FIFO, the FPGA design will read it and extract the I and Q data from the 32-bit sample. Up-sampling and frequency-shifting operations will be performed on the I and Q data before it is sent to the Radio420 RF front-end.
It is the RTDEx read rate in the FPGA, controlled by the upsampling block, that drives the flow control (or throttling) in the GNU Radio environment.
As the example shows, the new GNU Radio plug-in is flexible and easily handles different FPGA designs. The plug-in blocks look like those present in the Nutaq MBDK FPGA environment and they simplify setting up data flows between the host application and the FPGA design.
Using both the MBDK and GNU Radio environments, users can rapidly prototype and implement applications. The Nutaq blocks speed up the development process by removing concerns about the system interfaces. This lets users fully focus on their cutting-edge algorithms, modulations, and applications.