The purpose of an automatic gain control (AGC) algorithm in a digital receiver is to regulate the received signal strength at the inputs of the analog-to-digital converters (ADCs) in order to meet the signal-to-noise ratio (SNR) required for proper decoding. For example, if the received signal strength is weak at the antenna, the AGC algorithm boosts the receiver gain in order to minimize the noise and bring the signal level up to an acceptable SNR. Likewise, if the received signal strength is strong, the AGC algorithm attenuates the receiver gain in order to avoid signal clipping and nonlinear degradations.

In receivers that employ modern digital modulation techniques, like OFDM, the AGC corrects for long-term fading effects caused by shadowing. The algorithm used in the Nutaq OFDM reference design is able to adjust the gain of each receive antenna, on a packet-to-packet basis, thanks to the Nutaq FPGA blockset and Xilinx’s System Generator.

The algorithm itself is an integrate-and-dump function over 2048 samples, triggered by the block boundary detection algorithm. As soon as the block boundary detection algorithm detects an OFDM packet, the integrate-and-dump function starts, using the following equation to estimate the mean of the received signal power:

Equation to Estimate the Mean of the Received Signal Power

This mathematical equation is easily implemented with System Generator blocks, as shown in Figure 1:

Figure 1: AGC algorithm System Generator model

Figure 1: AGC algorithm System Generator model 

The red boxes show the instantaneous power calculation of the received complex signals on both antennas. The green boxes show the implementation of the moving average algorithm. It has an average length of 2048 samples and the division is easily implemented with an 11-bit bit shift operation. The orange box takes the control signal coming from the block boundary detection algorithm and starts counting up to 2048 before dumping the mean power of the received signal into a register. That value is compared to a user-defined threshold and the result of this comparison raises or lowers the gain of the variable gain amplifiers (VGAs) on the Nutaq FMC Radio420X, as shown in Figure 2:

Figure 2: Gain control part of the AGC algorithm

Figure 2: Gain control part of the AGC algorithm

In the red boxes, the mean powers of the received signals are compared to the user-defined threshold and this comparison will increase or decrease the value of a 6-bit resolution counter. The Nutaq FMC Radio420X blocks (green boxes) are configured in RX Gain Control Mode (Figure 3).

Figure 3: Nutaq FMC Radio420X FPGA control block settings

Figure 3: Nutaq FMC Radio420X FPGA control block settings

In RX Gain Control Mode, the Nutaq block only has two inputs: rx_gain and rx_gain_start. Figure 4 shows the block’s help documentation on the subject:

Figure 4: Nutaq’s FMC Radio420X help section for the rx_gain input signal

 Figure 4: Nutaq’s FMC Radio420X help section for the rx_gain input signal

The rx_gain input signal uses an unsigned 6-bit value to digitally control the receiver VGA gain, as shown in Figure 5 (red box):

Figure 5: Block diagram of the Nutaq FMC Radio420X card

Figure 5: Block diagram of the Nutaq FMC Radio420X card

The rx_gain_start signal is simply the enable signal that tells the Nutaq block to send the current value of rx_gain to the FMC Radio420X VGA.

This brief blog showed a simple and efficient way to implement an AGC algorithm using System Generator and the Nutaq blockset. This approach efficiently controls the mean received power of both antennas because you can directly update the FMC Radio420x’s VGA values from the FPGA, without any intermediaries. This ensures that the VGAs are updated before the next packet is received.

A QAM64 MIMO OFDY PHY layer reference design