In Part 1 of this series, we introduced the concept of sample time and data type. To validate the correct configuration of these settings, you can update your model (Ctrl-D) to directly see the configuration settings on the model itself. To enable the display of these configuration options, select the options shown below:

These are very useful as they let you see the configurations without having to check each block every time. Your model should look something like this:

Two distinct colours appear: green and red. Each color represents a specific sample time value. You can access the sample time legend by clicking Ctrl-J:

As you can see, we have the two colors assigned to specific sample time values. The important point here is the ratio between the different sample time values (see Part 1 for a detailed explanation). We can also see that the Repeat blocks change the color of their inputs, which basically means that the block oversamples by a factor of 2, moving from a sample time of 1 to a sample time value of 0.5.

The next step is to simulate our model to see that everything is working as expected. Personally, when simulating a Simulink model intended to generate FPGA code, I like to see my results in term of clock cycles. Open a scope and in the View > Configuration properties, configure the pop-up windows as follows:

The two important settings are Sample time and Time units. Sample time is the sample time of the scope and should equal the smallest sample time value of all the blocks (0.5 in our case). The Time units setting should be set to ‘None’. This way, the results will be unit-less, but we know that each step of 0.5 equals one clock cycle. I prefer this approach for two reasons. First, it’s definitely easier to analyze the results this way. Second, because the results are independent of the clock frequency that you will use later in order to make our model modular.

With these settings, let’s take a look at what should be observed at the output of the Sine wave block:

First, we can see that at time 100, we have a complete period for both I and Q signals. Also, if we zoom in to one specific value, we should see that we have the same value during two samples:

Looking closely, we can see that the 0 value is held from time 25 to time 26, which is expected from the sample time value of the Sine wave block. Now let’s take a look at the output of the interleaver:

We can easily distinguish the interleaving pattern of the I and Q signals. And, if we zoom in:

We can see that we have one value at time 18 and a different one at time 18.5, which is expected from a signal with a sample time of 0.5.

The last step is to create a subsystem that includes the processing blocks. This can easily be done by selecting the necessary blocks and right-clicking on Create Subsystem from Selection:

You should now have a box with four outputs:

HDL coder can now create HDL code for these specific subsystems. We will follow the HDL code generation process in Part 3 of this blog series.