A conventional analog zero-IF (intermediate frequency) in-phase and quadrature (I/Q) demodulator uses analog components to translate an RF signal to baseband analog I and Q signals before converting it to digital data samples. Low-quality analog RF components can cause a number of errors that degrade I/Q demodulator performance, including DC offset, I/Q gain imbalance, and I/Q phase imbalance. High-quality analog components in an I/Q demodulator reduce these errors but increase the cost of the wireless system's RF front-end. High-speed analog-to-digital converters (ADC) are now widely used as an alternative approach, pushing the analog I/Q demodulator into the digital domain in order to reduce errors caused by analog RF components. This blog post shows an example of how a digital I/Q demodulator pairs with a high-speed ADC sampling at an IF.

Digital I/Q demodulator

Figure 1shows the block diagram of a digital I/Q demodulator. The input IF signal, centered at 8 MHz, is sampled directly by a single high-speed ADC device. The IF samples are mixed with 8-MHz digital cosine and sine samples generated by a direct-digital synthesizer (DDS) to translate the signal to baseband. Filtering out the high-frequency component of the digital mixer output is required to obtain the design's baseband signal.

Figure 1: Digital I/Q demodulator

Figure 1: Digital I/Q demodulator

IF sampling with the ADAC250

A test model of the digital I/Q demodulator is shown in Figure 2. The design is clocked at 128 MHz from the ADAC250 module 

[1]. The interpolated I and Q symbols from the QPSK modulator are multiplexed at 128 Msps and then translated to IF-centered at 8 MHz. Multiplexing of the I and Q rails is used in order to take advantage of the multi-channel filtering of Xilinx’s finite-impulse-response (FIR) filter core. The final nominal sample rate is 64 Msps per I or Q rail. Note that the additive white Gaussian noise (AGWN) channel block between the DAC and the ADC block is used only for simulation purposes. It does not take into account the FPGA bitstream generation.

The digital I/Q demodulator uses a multiplier-less CORDIC-based [2] digital mixer to translate the input IF to the baseband signal, as shown in Figure 3.  The following block diagram of the digital I/Q demodulator contains several cascaded half-band and FIR decimation filters that reduce the sample rate.

Figure 2: Digital I/Q demodulator test model

Figure 2: Digital I/Q demodulator test model

Figure 3: Digital I/Q demodulator

Figure 3: Digital I/Q demodulator

Simulation results at the digital I/Q demodulator output provides similar I/Q waveforms to the I/Q rails at the transmit interpolation filter output, as shown in Figure 4. This simulation provides the expected I/Q waveforms when the receiver IF mixer has the same phase relationship as the transmitter IF mixer. If they are out-of-phase, the digital I/Q demodulator will provide unexpected results. Figure 5shows the simulation result of the digital I/Q demodulator output when both IF mixers are out-of-phase. Therefore, the receiver must have an ability to lock the receiver IF mixer to the incoming IF signals, sometimes called carrier recov­ery [3]. There are many well-known algorithms to resolve this problem and I will discuss them in a future blog post.

Figure 4: Expected digital I/Q demodulator output

Figure 4: Expected digital I/Q demodulator output

Figure 5: Unexpected digital I/Q demodulator output

Figure 5: Unexpected digital I/Q demodulator output

Conclusion

The use of IF sampling high-speed ADC and digital I/Q demodulator may reduce potential errors such as gain imbalance and DC offset when the IF to baseband translation is performed in analog domain. This blog post showed an example of IF sampling using ADA250 and an implementation of simple digital I/Q demodulation using Nutaq's Model-Based Design Kit (MBDK) [4] for illustration purposes.

References

[1]

Nutaq Inc. (2014) ADAC250. [Online]. http://www.nutaq.com/products/adac250

[2]

Wikipedia. (2014) CORDIC. [Online]. http:/http://www.nutaq.com.wikipedia.org/wiki/CORDIC

[3]

Wikipedia. Carrier Recovery. [Online]. http:/http://www.nutaq.com.wikipedia.org/wiki/Carrier_recovery

[4]

Nutaq Inc. (2014) Model-Based Design Kit (MBDK). [Online]. http://www.nutaq.com/software/model-based-design-kit