In the previous blog post in this series, we described the data throughput challenges and the limitations of the PCIe interface when building massive multiple-input/multiple-output (MIMO) systems. As a solution to these challenges, we introduced the Aurora interface and data transfer parallelization.
This blog post describes an example system based on an MTCA.4 chassis with rear-transition modules (RTM). We provide information about the RF front-end, the advanced mezzanine card (AMC) carrier board, the RTM, and how we designed the clocking to synchronize all the channels. We then conclude with the system’s data communication topology (briefly described in the previous blog).
General system description
The system consists of many subsystems, each of which handles a specific function:
- The Radio420M, a state-of-the-art radio front-end with two receive (RX) channels and two transmit (TX) channels, handles the heterodyning of the RF signal.
- Two Radio420M radio front-ends are connected to an AMC, the Perseus611X. Each Perseus611X has a Virtex-6 FPGA and 4 GB of RAM and supports four TX and four RX channels.
- Each Perseus AMC is installed in a MicroTCA.4 chassis equipped with RTMs. The RTMs provide interfaces that enable the required high-rate communication between the Perseus AMCs equipped with the radio heads and the rest of the system (over an Aurora link at rates around 16 Gbps). Seven miniSAS connectors are available on each RTM to access the Aurora interface. All the data can be sent and received by a master Perseus equipped with a larger FPGA that handles the heavy baseband processing.
- A quad-core i7 PC controls the whole system. A PCIe bus handles low-latency communication for control purposes throughout the system.
Figure 1: A 100×100 massive MIMO system
The Radio420M FPGA mezzanine card (FMC) is used as the radio front-end (Figure 2). It’s a powerful multi-mode software-defined radio (SDR) transceiver with two channels (2 TX and 2 RX). Build around the multi-standard, multi-band Lime Microsystems LMS6002D RF transceiver IC, the Radio420X supports broadband coverage as well as frequency-division duplexing (FDD) and time-division duplexing (TDD) full duplex modes of operation.
Figure 3 shows a functional diagram of the radio interface. The front-end converts bandpass to baseband with no intermediate frequency (IF). I and Q samples are sent to the FPGA for baseband processing or for transfer to another device. The Radio420 is immediately ready achieve its maximum performance as it includes auto-calibration features (IQ imbalance, DC offset and LO-leakage).
Figure 2: Radio420M 2×2 SDR front-end
Figure 3: Radio420M functional block diagram
The Radio420M has the following key features:
- Software-adjustable amplifiers for a wide dynamic range (up to 80 dB)
- Frequency range of 300 to 3800 MHz (software-tunable)
- Selectable bandwidth from 1.5 to 28 MHz (software-selectable)
- 14 selectable bandpass filters to handle interference (with full bypass option)
- Auto-calibration (LO-leakage, DC offset, IQ imbalance)
- Software-defined amplifiers
- Internal reference clock of 30.72 MHz
- Pulse per second (PPS) receiver for crystal oscillator’s synchronization in-phase (enables GPS-based synchronization)
- I and Q samples sent to the FPGA through the FMC connector at full rate
FPGA unit with logic modules and RAM memory
Figure 4: Perseus6110 AMC with Virtex-6 FPGA
The Perseus6111 and Perseus6113 are double-width AMCs with Virtex-6 LX550T or SX475T FPGAs and two FMC high-pin-count (HPC) sites (to connect the radio front-ends). Each Perseus611X can handle two Radio420M FMCs (thus four transceivers per card). The Perseus611X serves as a processing unit as well as an enabler for the Aurora interface via the RTM modules. The Perseus611X is equipped with 4 GB of SDRAM. The FPGA modules are able access this memory at a very high speed via the included the record/playback IP core. Finally, the Perseus611X contains the logic to operate the radio front-end and set the RF parameters dynamically (for example, frequency, bandwidth, amplification of the signal, and high speed AGC).
The Perseus611X has the following key features:
- Virtex-6 FPGA (SX475T and LX550T)
- Real-time data exchange (RTDEx) module for handling the PCIe and Gigabit Ethernet interfaces for control and data exchange
- Support for 7x Aurora communication channels (Aurora 4x – 16 Gbps) over miniSAS connectors
- Control module for the Radio420 RF front-end (for enabling SDR features and auto-calibration)
- Programmable logic space for the user’s algorithm
- Support FPGA modules for time stamping and PPS synchronization of data transfers
- SDRAM memory with record/playback module on the FPGA
The MTCA.4 RTM for the Perseus 611X (Figure 5) expands the I/O capability of the Perseus611X. On the back plate, 7 miniSAS connectors are available, each providing an Aurora 4x high speed interface (16 Gbps).
Figure 5: Perseus611X RTM
Channel synchronization (phase and frequency)
An external clock from the clock generator (“Clk generator” in Figure 6) is fed to each chassis. The CLK IN module feeds the clock signal to the MicroTCA carrier hub (MCH) which, in turn, distributes it to the Perseus cards throughout the chassis via the backplane. This way, all the Perseus cards use the same clock. The MCH is equipped with a GPS receiver that timestamps the digital samples to facilitate MAC layer development, providing it with the right tools to send and receive data bursts at the right time. The red path in Figure 6 illustrates the clocking scheme and the blue path represents the pulse-per-second used for timestamping.
Figure 6: Clocking diagram
Data communication topology
The Perseus611x cards are organized in subgroups. Each subgroup is constituted of four Perseus6111 cards. Each chassis contains three subgroups. Every is connected to a subgroup master Perseus6111 and each subgroup master is connected to the system master, as shown in Figure 7. All connection are made using miniSAS connectors at the back panel of the system and can easily be changed at any time. The data rate in these links is around 16 Gbps.
Each RTM of the system has seven miniSAS connectors. All of the Perseus cards within the subgroup except for the master Perseus have six free miniSAS connectors free for connecting the other members of the subgroup in a mesh architecture. This allows upstream distributed processing to be done in the subgroup.
Figure 7: Data communication topology
This blog post showed how Nutaq handles the challenge of very high throughputs for real-time baseband processing in a massive MIMO system. It described the radio front-end, Nutaq’s unique Perseus611X as the processing board, the rear transition modules, and the system clocking. In the next blog post in this series, we will describe how to improve the system by providing it with a huge processing unit for heavy baseband processing.