We saw in the first part of this blog series that Radio420x Tx/Rx phase-locked loop (PLL) programming time is on average 32.4 µs with a 100 MHz Serial Peripheral Interface (SPI) bus clock. The 32.4 µs time comprises 12 SPI register write commands in order to:

  1. Set the frequency range (FRANGE) value
  2. Set the integer and fractional part of the divider
  3. Set the VCO CAP, charge pump current (Icp), and charge pump offset current (Ioff)

In some cases, the hop sequence can be designed to avoid changing the FRANGE on each hop, which leads to a configuration time lower than 32.4 µs.

PLL configuration time is not the only factor to take into account when implementing FHSS on the Radio420x. After the configuration commands are sent, the PLL settling time also has a determinant role in the blanking interval (the time during a hop when data cannot be received or transmitted). PLL settling time is an internal parameter of the LMS6002D, the direct-conversion RF integrated circuit (RFIC) from Lime Microsystems used in the Radio420x.

The LMS6002D datasheet (Table 5 on page 4) shows the typical settling time for the chip’s PLL. Settling time is described as the time required for the outputs to stabilize after a PLL programming command is recieved via the SPI interface. The typical settling given is 20 µs for a 50 kHz PLL loop bandwidth.

The 20 µs required for the PLL to settle after being programmed adds up to the 32.4 µs needed to send the programming commands, resulting in a total of 52.4 µs for the blanking interval (typical). Such a short blanking interval makes the Radio420x suitable for FHSS applications like as Bluetooth (< 230 µs blanking interval).

Additionally, some PLL settling time measurements on the LMS6002D were performed and published by Lime Microsystems with 100 and 200 KHz loop filters:

https://07989609037669312839.googlegroups.com/attach/aa9e4d12c8ad8ae5/LMS6002D_RX_PLL_locking_time_v2.pdf?part=4&vt=ANaJVrGee-jEScQIFdh2NDVwgiuBej2xycKVNpcIBABpq2CaUshmyqDhbG1-hpK8d5s2SdZ9lvtYtZ-6dJCLV9zcGVVNGUnpScO_vu0GK-LvRv4tj-M-Icc

These measurements, rather than being done in a frequency hoping context, were done in a time-division duplexing (TDD) mode, and measured the elapsed time between the reception of the Tx to the Rx switching command via the SPI interface, and time at which the PLL settles to its Rx frequency. When Rx PLL settles we should expect DC at the RX analog output.

Here are the results:

Loop filter: 100 KHz

Charge pump current: 1200 µA

Measured settling time: 38.6 µs

Copyright Lime Microsystems (link)

Loop filter: 200 KHz

Charge pump current: 1200 µA

Measured settling time: 23.0 µs

Copyright Lime Microsystems (link)

Loop filter: 200 KHz

Charge pump current: 2400µA

Measured settling time: 8.0 µs

Copyright Lime Microsystems (link)

These results suggest that it is possible to reduce the LMS6002D PLL settling time by tuning the  PLL loop filter.