In my previous blog post, I mentioned a common method for bit error rate (BER) measurements in digital communication systems: pseudo-random binary sequences (PRBS). PRBS has excellent properties, namely a randomized, balanced number of ones and zeros over the maximum sequence period. 

In this blog post, I demonstrate BER measurement of a simple BPSK communication chain using PRBS9 (sometimes called PN9 sequences) with Xilinx’s System Generator 

[1] in conjunction with Nutaq’s Model-Based Design Kit (MBDK) [2].

Generation of PN9 sequences

PN9 has taps at the 9th and 5th positions and can be represented as the following polynomial:

x+ x1

A feedback polynomial can be configured in either a Fibonacci or Galois-style [3], which is available in System Generator as shown in Figure 1. An equivalent of the Fibonacci PN9 sequence generator in System is shown in Figure 2.

Figure 1: Fibonacci PN9 configuration

Figure 1: Fibonacci PN9 configuration

Figure 2: Fibonacci PN9 configuration

Figure 2: Fibonacci PN9 configuration

BPSK BER measurement model

Figure 3 shows a simple binary phase-shift keying (BPSK) digital communication chain with PN9 used as a random bit generator in both the transmitter and receiver. At the transmitter, the baseband BPSK modulated symbols are translated to an intermediate frequency (IF) of 8 MHz then converted to an analog signal by using the digital-to-analog converter (DAC) in the ADAC250 module [4]. The BPSK modulated analog signal passes into a noisy channel for simulation purposes.  

Figure 3: BER measurement in BPSK chain using PN9 sequence

Figure 3: BER measurement in BPSK chain using PN9 sequence

Figure 4: IF digital down-converter

Figure 4: IF digital down-converter

Figure 5: BPSK Costas loop simulation

Figure 5: BPSK Costas loop simulation

At the receiver, the noisy BPSK modulated IF signal is sampled by the analog-to-digital converter (ADC) of the ADAC250 module, followed by an IF digital down-conversion (DDC) block to obtain the BPSK symbols. The IF DDC contains an IF mixer centered at 8 MHz with a Costas loop circuit to correct for  phase/frequency errors and a decimator, as shown in Figure 4. The Costas loop quickly locks to zero phase errors after first few BPSK symbols have received, as shown in Figure 5(i.e. the Q component is approximately zero, as expected).

The BPSK demodulator block contains a joint BPSK symbol bit slicer and an 1-bit correlator to control the PN9 burst valid generation block, as shown in Figure 6.

Figure 6: BPSK demodulator

Figure 6: BPSK demodulator

Figure 7: PN9 generation at BPSK receiver

Figure 7: PN9 generation at BPSK receiver

Figure 7shows a local PN9 generator that automatically synchronizes with the demodulated incoming bit stream from the BPSK demodulator in order to compute the BER. The same PN9 polynomial configuration must be used at the receiver. If there are too many consecutive bits corrupted by the channel or bad synchronization, this block re-initializes the initial state of local PN9 generator before generating a reference PN9 sequence.

A simulation of the BPSK BER measurement using PN9 sequences is shown in Figure 8. The bit counter and bit error counter start to count as soon as the local PN9 generator output locks to the incoming bit stream. I generated a burst error at the transmitter during simulation in order to toggle the ‘manual switch’ shown in Figure 3. As soon as the receiver detects the burst error, the PN9 lock status signal goes low and the error bit counts up until the PN9 lost synchronization goes high. In this situation, the receiver tries to reinitialize the PN9 until it locks to the incoming bit stream.

Figure 8: Simulation of BER measurement using PN9 sequence

Figure 8: Simulation of BER measurement using PN9 sequence

Conclusion

This blog post showed a model-based implementation of a simple BPSK chain for BER measurement with PBRS sequences using System Generator and Nutaq’s MBDK. A PN9 sequence was used in this blog post for demonstration purposes.

References

[1]

Wikipedia. (2014) Linear feedback shift register. [Online]. http:/http://www.nutaq.com.wikipedia.org/wiki/Linear_feedback_shift_register

[2]

Xilinx Inc. (2012) System Generator User Guide. [Online]. http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/sysgen_user.pdf

[3]

Nutaq Inc. (2014) Model-Based Design Kit (MBDK). [Online]. http://www.nutaq.com/software/model-based-design-kit