Accelerating Algorithm Development Using Multichannel Recording Tools
In designing an FPGA-based pulse processing algorithm, the standard development cycle makes use of a number of software modeling and simulation tools to refine the algorithm before implementing it in a real system. In this post, we’ll discuss this development process in detail, and we’ll see that adding multichannel recording tools like Nutaq’s Record/Playback module (see related blog) can accelerate development by incorporating the digitized imperfections of the pulse shape and DAQ of the real system early in the cycle.
The Standard Development Cycle
The standard development cycle for multichannel pulse processing algorithms generally consists of four phases:
- Design and validate the algorithms using a simulation modeling tool like Simulink® from MathWorks®.
- Generate the FPGA fabric from the Simulink model using System Generator for DSP™ from Xilinx®.
- Validate the hardware implementation through hardware-in-the-loop (HIL) simulation or co-simulation.
- Implement the algorithm in the final hardware.
Design and Validate the Algorithm Using Simulink
With Simulink there are no restrictions on using floating-point processing in the algorithm implementation. The designer can focus on the pure behavior of the algorithm. To drive the behavioral development of the algorithms, the designer uses simulated pulse-shape test vectors. However, these test vectors may not be completely accurate with the end-system multichannel DAQ equipment.
Generate the FPGA Fabric Using System Generator
Converting the algorithm to FPGA fabric takes advantage of the inherent advantages of parallel computing and simplified multichannel processing. On the other hand, it also introduces the limitations that come along FPGA architecture, such as speed constraints and the need to adapt the algorithm to cope with the fixed-point processing of the FPGA.
The converted algorithm is validated with the same multichannel pulse-shape test vectors used in the design phase.
Validate the FPGA Implementation
This step uses hardware-in-the-loop (HIL) simulation or co-simulation to validate the FPGA code implementation while using the same Simulink initial test vectors. It can also be used to ease the hardware implementation by allowing the transition to happen in a step-by-step manner. This step also introduces interactions with a host PC, and its possible limitations (latency, bandwidth restriction, and so on) for algorithm adaptation. In addition, image processing and parameter control functionality on the PC, and its interaction with algorithms on the FPGA side, may create the need for more refinements to the original algorithm.
Implement the Algorithm in the Final Hardware
Lastly, the final hardware implementation will include the real-life inputs and outputs through the integration with the end-system detectors and multichannel DAQ. Note that up to this point in the development process, the imperfections of the final multichannel DAQ system haven’t been considered in the algorithm. This could have a dramatic impact on the development time by causing design iterations if adjustments to the algorithm are needed to compensate for factors like channel-to-channel digitizer phase alignment, ADC behaviors, the pulse shape (which depends on specific detectors), and so on.
Where Multichannel Recording Tools Come In
Between each phase in the model-based design process, more and more variables are introduced that must be accounted for in the algorithm design, as shown in the following figure:
The variables in the final phase (analog domain) are much harder to predict and control than the other variables, being deeply related to the real-life analog front-end detector behaviors, and all the imperfections associated with the conversion of the multichannel digital samples from the DAQ system. By using a multichannel recording tool and injecting the imperfections of the final system into the original algorithm design, the designer can account for these variables much sooner in the development process, as the following figure illustrates:
Multichannel Recording Tools Accelerate Development
As we’ve discussed, multichannel recording tools can really accelerate the development of FPGA-based pulse processing applications by directly including digitized pulse shape imperfections and multichannel DAQ characteristics from the actual final system at the algorithm design stage. These characteristics have a direct impact on algorithms development, so accounting for them as early as possible in the design process can save a significant amount of time.
To learn more about Nutaq’s model-based design tools and Record/Playback module, check out our previous blog post and the MBDK page on our website.